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74670 の電気的特性と機能

74670のメーカーはFairchild Semiconductorです、この部品の機能は「3-STATE 4-by-4 Register File」です。


製品の詳細 ( Datasheet PDF )

部品番号 74670
部品説明 3-STATE 4-by-4 Register File
メーカ Fairchild Semiconductor
ロゴ Fairchild Semiconductor ロゴ 




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74670 Datasheet, 74670 PDF,ピン配置, 機能
August 1986
Revised March 2000
DM74LS670
3-STATE 4-by-4 Register File
General Description
These register files are organized as 4 words of 4 bits
each, and separate on-chip decoding is provided for
addressing the four word locations to either write-in or
retrieve data. This permits writing into one location, and
reading from another word location, simultaneously.
Four data inputs are available to supply the word to be
stored. Location of the word is determined by the write
select inputs A and B, in conjunction with a write-enable
signal. Data applied at the inputs should be in its true form.
That is, if a high level signal is desired from the output, a
high level is applied at the data input for that particular bit
location. The latch inputs are arranged so that new data
will be accepted only if both internal address gate inputs
are HIGH. When this condition exists, data at the D input is
transferred to the latch output. When the write-enable
input, GW, is HIGH, the data inputs are inhibited and their
levels can cause no change in the information stored in the
internal latches. When the read-enable input, GR, is HIGH,
the data outputs are inhibited and go into the high imped-
ance state.
The individual address lines permit direct acquisition of
data stored in any four of the latches. Four individual
decoding gates are used to complete the address for read-
ing a word. When the read address is made in conjunction
with the read-enable signal, the word appears at the four
outputs.
This arrangement—data entry addressing separate from
data read addressing and individual sense line — elimi-
nates recovery times, permits simultaneous reading and
writing, and is limited in speed only by the write time (27 ns
typical) and the read time (24 ns typical). The register file
has a non-volatile readout in that data is not lost when
addressed.
All inputs (except read enable and write enable) are buff-
ered to lower the drive requirements to one normal Series
DM74LS load, and input clamping diodes minimize switch-
ing transients to simplify system design. High speed, dou-
ble ended AND-OR-INVERT gates are employed for the
read-address function and have high sink current, 3-STATE
outputs. Up to 128 of these outputs may be wire-AND con-
nected for increasing the capacity up to 512 words. Any
number of these registers may be paralleled to provide n-
bit word length.
Features
s For use as:
Scratch pad memory
Buffer storage between processors
Bit storage in fast multiplication designs
s Separate read/write addressing permits simultaneous
reading and writing
s Organized as 4 words of 4 bits
s Expandable to 512 words of n-bits
s 3-STATE versions of DM74LS170
s Fast access times 20 ns typ
Ordering Code:
Order Number Package Number
Package Description
DM74LS670M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS670N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation DS006436
www.fairchildsemi.com

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74670 pdf, ピン配列
Absolute Maximum Ratings(Note 4)
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range
65°C to +150°C
Note 4: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
Parameter
Min
Nom
Max
Units
VCC Supply Voltage
4.75 5 5.25 V
VIH HIGH Level Input Voltage
2
V
VIL LOW Level Input Voltage
0.8 V
IOH HIGH Level Output Current
2.6
mA
IOL LOW Level Output Current
24 mA
tW Write Enable Pulse Width (Note 5)
25
ns
tSU Setup Time
Data
10
(Note 5)(Note 6)
WA, WB
15
ns
tH Hold Time
Data
15
(Note 5)(Note 6)
WA, WB
5
ns
tLATCH
Latch Time for New Data (Note 5)(Note 7)
25
ns
TA Free Air Operating Temperature
0
70 °C
Note 5: TA = 25°C and VCC = 5V.
Note 6: Times are with respect to the Write-Enable input. Write-Select time will protect the data written into the previous address. If protection of data in the
previous address, tSETUP (WA, WB) can be ignored. As any address selection sustained for the final 30 ns of the Write-Enable pulse and during tH (WA, WB)
will result in data being written into that location. Depending on the duration of the input conditions, one or a number of previous addresses may have been
written into.
Note 7: Latch time is the time allowed for the internal output of the latch to assume the state of new data. This is important only when attempting to read from
a location immediately after that location has received new data.
3 www.fairchildsemi.com


3Pages


74670 電子部品, 半導体
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
www.fairchildsemi.com
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共有リンク

Link :


部品番号部品説明メーカ
74670

3-STATE 4-by-4 Register File

Fairchild Semiconductor
Fairchild Semiconductor
74670

4-BY-4 REGISTER FILES

National Semiconductor
National Semiconductor


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