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HD74HC4053 の電気的特性と機能

HD74HC4053のメーカーはRenesasです、この部品の機能は「Triple 2-channel Analog Multiplexers/Demultiplexers」です。


製品の詳細 ( Datasheet PDF )

部品番号 HD74HC4053
部品説明 Triple 2-channel Analog Multiplexers/Demultiplexers
メーカ Renesas
ロゴ Renesas ロゴ 




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HD74HC4053 Datasheet, HD74HC4053 PDF,ピン配置, 機能
HD74HC4052, HD74HC4053
Dual 4-channel Analog Multiplexers/Demultiplexers
Triple 2-channel Analog Multiplexers/Demultiplexers
REJ03D0649-0200
(Previous ADE-205-536)
Rev.2.00
Mar 30, 2006
Description
HD74HC4052: This device connects together the outputs of 4 switches in two sets, thus achieving a pair of 4 channel
multiplexers. The binary code placed on the A, and B select lines determine which switch in each 4 channel section is
“on”, connecting one of the four inputs in each section to its common output. This enables the implementation of a 4
channel differential multiplexer.
HD74HC4053: This device contains 6 switches whose outputs are connected together in pairs, thus implementing a
triple 2 channel multiplexer, or the equivalent of 3 single-pole-double throw configuration. Each of the A, B, or C
select lines independently controls one pair of switches, selecting one of the two switches to be “on”.
Features
High Speed Operation
Wide Operating Voltage: VCC = 2 to 6 V
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74HC4052P
HD74HC4053P
DILP-16 pin
PRDP0016AE-B
(DP-16FV)
P
HD74HC4052FPEL
SOP-16 pin (JEITA)
HD74HC4053FPEL
PRSP0016DH-B
(FP-16DAV)
FP
HD74HC4052RPEL
SOP-16 pin (JEDEC)
HD74HC4053RPEL
PRSP0016DG-A
(FP-16DNV)
RP
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
Function Table
Control Inputs
Select
Inhibit
C*1
B
LLL
LLL
L LH
L LH
LHL
LHL
L HH
L HH
HXX
Note: 1. Not applicable for HD74HC4052
X = Irrelevant
A
L
H
L
H
L
H
L
H
X
HD74HC4052
Y0 X0
Y1 X1
Y2 X2
Y3 X3
ON Switch
HD74HC4053
Z0 Y0
Z0 Y0
Z0 Y1
Z0 Y1
Z1 Y0
Z1 Y0
Z1 Y1
Z1 Y1
X0
X1
X0
X1
X0
X1
X0
X1
Rev.2.00 Mar 30, 2006 page 1 of 11

1 Page





HD74HC4053 pdf, ピン配列
HD74HC4052, HD74HC4053
Block Diagram
HD74HC4052
Inh
A
B
X0
X1
X2
X3
Y0
Y1
Y2
Y3
VCC
Level
Converter
Binary to
1-of-4 Decoder
with Inhibit
GND
VEE
HD74HC4053
VCC
Inh
A Level
B Converter
C
Binary to 1-of-2
Decoder with
Inhibit
GND
VEE
X0
X1
Y0
Y1
Z0
Z1
X
Y
X
Y
Z
Absolute Maximum Ratings
Item
Supply voltage
Control input voltage
Switch I/O voltage
Supply current
Switch I/O current (per pin)
Control input diode current
Switch I/O diode current
Power dissipation
Storage temperature range
(VCC)
(GND)
Symbol
VCC
VCC – VEE
VIN
VI/O
ICC
IGND
II/O
IIK
IIOK
PT
Tstg
Rating
–0.5 to +7.0
–0.5 to +7.0
GND – 0.5 to VCC + 0.5
VEE – 0.5 to VCC + 0.5
+50
–50
±25
±20
±20
500
–65 to +150
Rev.2.00 Mar 30, 2006 page 3 of 11
Unit
V
V
V
V
mA
mA
mA
mA
mA
mW
°C


3Pages


HD74HC4053 電子部品, 半導体
HD74HC4052, HD74HC4053
Test Circuit
Maximum Control Frequency
VC VCC
Vin VCC
VCC
Vout
VEE GND
RL =
1 k
CL =
15 pF
VCC
VC
0V
Vout
Vcc/2
Cross talk (Between Any Two Switches)
VCC
VCC
Vin
(ON)
Vout1
fin
0.1 µF Rin =
600
VEE
GND
RL =
600
VCC/2
VCC
CL =
50 pF
Vin
(Sine Wave)
(Vin = 0 dBm, f = 1 MHz)
Rin =
600
VCC
(OFF)
Vout2
VEE GND
RL =
600
VCC/2
Cross talk (Control Input to Switch Output)
CL =
50 pF
VCC
VC
Vin
Rin =
600
VCC Vout
VEE GND
RL =
600
VCC/2
VCC/2
CL =
50 pF
VCC
GND
tr tf
90%
10%
(f = 1 MHz)
tr = tr = 6 ns
Rev.2.00 Mar 30, 2006 page 6 of 11

6 Page



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共有リンク

Link :


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Renesas
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HD74HC4052FPEL

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