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UPD424210 の電気的特性と機能

UPD424210のメーカーはNECです、この部品の機能は「4 M-BIT DYNAMIC RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD424210
部品説明 4 M-BIT DYNAMIC RAM
メーカ NEC
ロゴ NEC ロゴ 




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UPD424210 Datasheet, UPD424210 PDF,ピン配置, 機能
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD424210
4 M-BIT DYNAMIC RAM
256K-WORD BY 16-BIT, EDO,
BYTE READ/WRITE MODE
Description
The µPD424210 is a 262,144 words by 16 bits CMOS dynamic RAM with optional EDO.
EDO is a kind of page mode and is useful for the read operation.
The µPD424210 is packaged in 44-pin plastic TSOP (II) and 40-pin plastic SOJ.
Features
• EDO (Hyper page mode)
• 262,144 words by 16 bits organization
• Single power supply
+5.0 V ± 10 % : µPD424210-60, 424210-70
+5.0 V ± 5 % : µPD424210-60-G
Part number
µPD424210-60
µPD424210-60-G
µPD424210-70
Power consumption
Active (MAX.)
880 mW
840 mW
825 mW
Access time
(MAX.)
60 ns
60 ns
70 ns
R/W cycle time
(MIN.)
104 ns
104 ns
124 ns
EDO (Hyper page mode)
cycle time (MIN.)
25 ns
25 ns
30 ns
Part number
µPD424210-60
µPD424210-70
µPD424210-60-G
Refresh cycle
512 cycles/8 ms
512 cycles/8 ms
Refresh
CAS before RAS refresh,
RAS only refresh,
Hidden refresh
Power consumption at standby
(MAX.)
5.5 mW
(CMOS level input)
5.25 mW
(CMOS level input)
The information in this document is subject to change without notice.
Document No. M12941EJ1V0DS00 (1st edition)
Date Published September 1997 N
Printed in Japan
©
1997

1 Page





UPD424210 pdf, ピン配列
Pin Configurations (Marking Side)
44-pin Plastic TSOP (II) (400 mil)
µPD424210G5-7JF
VCC 1
I/O1 2
I/O2 3
I/O3 4
I/O4 5
VCC 6
I/O5 7
I/O6 8
I/O7 9
I/O8 10
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
13
14
15
16
17
18
19
20
21
22
44 GND
43 I/O16
42 I/O15
41 I/O14
40 I/O13
39 GND
38 I/O12
37 I/O11
36 I/O10
35 I/O9
32 NC
31 LCAS
30 UCAS
29 OE
28 A8
27 A7
26 A6
25 A5
24 A4
23 GND
µPD424210
40-pin Plastic SOJ (400 mil)
µPD424210LE
VCC
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 GND
39 I/O16
38 I/O15
37 I/O14
36 I/O13
35 GND
34 I/O12
33 I/O11
32 I/O10
31 I/O9
30 NC
29 LCAS
28 UCAS
27 OE
26 A8
25 A7
24 A6
23 A5
22 A4
21 GND
A0 to A8
: Address Inputs
[Row: A0 to A8, Column: A0 to A8]
I/O1 to I/O16 : Data Inputs/Outputs
RAS
: Row Address Strobe
UCAS
: Column Address Strobe (upper)
LCAS
: Column Address Strobe (lower)
WE : Write Enable
OE : Output Enable
VCC : Power Supply
GND
: Ground
NC : No Connection
3


3Pages


UPD424210 電子部品, 半導体
µPD424210
Hyper Page Mode (EDO)
The hyper page mode (EDO) is a kind of page mode with enhanced features. The two major features of the
hyper page mode (EDO) are as follows.
1. Data output time is extended.
In the hyper page mode (EDO), the output data is held to the next CAS cycle’s falling edge, instead of the rising
edge. For this reason, valid data output time in the hyper page mode (EDO) is extended compared with the fast
page mode (= data extend function). In the fast page mode, the data output time becomes shorter as the CAS
cycle time becomes shorter. Therefore, in the hyper page mode (EDO), the timing margin in read cycle is larger
than that of the fast page mode even if the CAS cycle time becomes shorter.
2. The CAS cycle time in the hyper page mode (EDO) is shorter than that in the fast page mode.
In the hyper page mode (EDO), due to the data extend function, the CAS cycle time can be shorter than in the
fast page mode if the timing margin is the same.
Taking a device whose tRAC is 60 ns as an example, the CAS cycle time in the fast page mode is 25 ns while that
in the fast page mode is 40 ns.
In the hyper page mode (EDO), read (data out) and write (data in) cycles can be executed repeatedly during one
RAS cycle. The hyper page mode (EDO) allows both read and write operations during one cycle.
The following shows a part of the hyper page mode (EDO) read cycle. Specifications to be observed are described
in the next page.
VIH
RAS VIL
Hyper Page Mode (EDO) Read Cycle
tHPC
tOFR
VIH
CAS VIL
tOFC
Address VIH
VIL
VIH
WE
VIL
VIH
OE VIL
I/O
VOH
VOL
Row
Col.A
tRAC
tAA
tCAC
tOCH
tOEA
Col.B
tAA
tCAC
Col.C
tAA
tCAC
tRRH
tRCH
tWPZ
tCHO
tOEP
tOCH
tOEP
tOEA
tCHO
tWEZ
Hi - Z
tOLZ
tCLZ
tDHC
tOEZ
tCLZ tOEZ
tOEZ
Data out A
Data out B
Data out C
Data out C Hi - Z
6

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
UPD424210

4M-Bit DRAM

NEC Electronics
NEC Electronics
UPD424210

4 M-BIT DYNAMIC RAM

NEC
NEC
UPD424210-60

4 M-BIT DYNAMIC RAM

NEC
NEC
UPD424210-60G

4 M-BIT DYNAMIC RAM

NEC
NEC


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