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AS4C16M16D1-5TCN の電気的特性と機能

AS4C16M16D1-5TCNのメーカーはAlliance Semiconductorです、この部品の機能は「16M x 16 bit DDR Synchronous DRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 AS4C16M16D1-5TCN
部品説明 16M x 16 bit DDR Synchronous DRAM
メーカ Alliance Semiconductor
ロゴ Alliance Semiconductor ロゴ 




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AS4C16M16D1-5TCN Datasheet, AS4C16M16D1-5TCN PDF,ピン配置, 機能
AS4C16M16D1
16M x 16 bit DDR Synchronous DRAM (SDRAM)
Alliance Memory Confidential
Advanced (Rev. 1.1, Sep. /2011)
Features
Fast clock rate: 200MHz
Differential Clock CK & CK
Bi-directional DQS
DLL enable/disable by EMRS
Fully synchronous operation
Internal pipeline architecture
Four internal banks, 4M x 16-bit for each bank
Programmable Mode and Extended Mode registers
- CAS Latency: 2, 2.5, 3
- Burst length: 2, 4, 8
- Burst Type: Sequential & Interleaved
Individual byte-write mask control
DM Write Latency = 0
Auto Refresh and Self Refresh
8192 refresh cycles / 64ms
Operating temperature range
- Commercial (0 ~ 70°C)
- Industrial (-40 ~ 85°C)
Precharge & active power down
Power supplies: VDD & VDDQ = 2.5V 0.2V
Interface: SSTL_2 I/O Interface
Package: 66 Pin TSOP II, 0.65mm pin pitch
- Pb free and Halogen free
Package: 60-Ball, 8x13x1.2 mm (max) TFBGA
- Pb free and Halogen Free
Overview
The AS4C16M16D1 SDRAM is a high-speed CMOS
double data rate synchronous DRAM containing 256 Mbits.
It is internally configured as a quad 4M x 16 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CK). Data outputs occur
at both rising edges of CK and CK .d Read and write
accesses to the SDRAM are burst oriented; accesses start
at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses
begin with the registration of a BankActivate command
which is then followed by a Read or Write command. The
AS4C16M16D1 provides programmable Read or Write
burst lengths of 2, 4, or 8. An auto precharge function may
be enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence. The refresh
functions, either Auto or Self Refresh are easy to use. In
addition, AS4C16M16D1 features programmable DLL
option. By having a programmable mode register and
extended mode register, the system can choose the most
suitable modes to maximize its performance. These
devices are well suited for applications requiring high
memory band-width, result in a device particularly well
suited to high performance main memory and graphics
applications.
Table 1.Ordering Information
Part Number
Clock Data Rate Package Temperature Temp Range
AS4C16M16D1-5TCN 200MHz 400Mbps/pin 66pin TSOPII Commercial 0 ~ 70°C
AS4C16M16D1-5TIN 200MHz 400Mbps/pin 66pin TSOPII Industrial -40 ~ 85°C
AS4C16M16D1-5BCN 200MHz 400Mbps/pin 60ball TFBGA Commercial 0 ~ 70°C
AS4C16M16D1-5BIN 200MHz 400Mbps/pin 60ball TFBGA Industrial -40 ~ 85°C
T: indicates TSOP II package
B: indicates TFBGA package
C: indicates Commercial temp.
I: indicates Industrial temp.
N: indicates lead free ROHS
Alliance Memory, Inc.
551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory, Inc. reserves the right to change products or specification without notice.

1 Page





AS4C16M16D1-5TCN pdf, ピン配列
Figure 2. Block Diagram
CK
CK
CKE
DLL
CLOCK
BUFFER
CS
RAS
CAS
WE
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
A10/AP
COLUMN
COUNTER
A0
A9
A11
A12
BA0
BA1
LDQS
UDQS
DQ0
DQ15
ADDRESS
BUFFER
REFRESH
COUNTER
DATA
STROBE
BUFFER
MODE
REGISTER
DQ
Buffer
LDM
UDM
AS4C16M16D1
4M x 16
CELL ARRAY
(BANK #0)
Column Decoder
4M x 16
CELL ARRAY
(BANK #1)
Column Decoder
4M x 16
CELL ARRAY
(BANK #2)
Column Decoder
4M x 16
CELL ARRAY
(BANK #3)
Column Decoder
Alliance Memory, lnc. Confidential
3
Rev. 1.1
Sep. /2011


3Pages


AS4C16M16D1-5TCN 電子部品, 半導体
AS4C16M16D1
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CK. Table 3
shows the truth table for the operation commands.
Table 3. Truth Table (Note (1), (2))
Command
State CKEn-1 CKEn DM BA0,1 A10 A0-9, 11-12 CS RAS CAS WE
BankActivate
Idle(3) H X X V
Row address
LL H H
BankPrecharge
Any H X X V L X L L H L
PrechargeAll
Any H X X X H X L L H L
Write
Write and AutoPrecharge
Active(3)
Active(3)
H
H
X X V L Column address L H L L
XX VH
(A0 ~ A8)
LH L L
Read
Read and Autoprecharge
Active(3)
Active(3)
H
H
X X V L Column address L H L H
XX VH
(A0 ~ A8)
LH L H
Mode Register Set
Idle H X X
OP code
LL L L
Extended MRS
Idle H X X
OP code
LL L L
No-Operation
Any H X X X X X L H H H
Burst Stop
Active(4) H
XX XX
X
LH H L
Device Deselect
Any H X X X X X H X X X
AutoRefresh
Idle H H X X X X L L L H
SelfRefresh Entry
Idle H L X X X X L L L H
SelfRefresh Exit
Idle L H X X X X H X X X
(SelfRefresh)
LH H H
Precharge Power Down
Idle H L X X X
X
HX X X
Mode Entry
LH H H
Precharge Power Down
Any L H X X X
X
HX X X
Mode Exit
(PowerDown)
LH H H
Active Power Down Mode Active
H
LXXX
X
HX X X
Entry
LV V V
Active Power Down Mode
Any
L HX XX
X
HX X X
Exit
(PowerDown)
LH H H
Data Input Mask Disable Active H X L X X X X X X X
Data Input Mask Enable(5) Active H X H X X X X X X X
Note: 1. V=Valid data, X=Don't Care, L=Low level, H=High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BA signal.
4. Device state is 2, 4, and 8 burst operation.
5. LDM and UDM can be enabled respectively.
Alliance Memory, lnc. Confidential
6
Rev. 1.1
Sep. /2011

6 Page



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部品番号部品説明メーカ
AS4C16M16D1-5TCN

16M x 16 bit DDR Synchronous DRAM

Alliance Semiconductor
Alliance Semiconductor


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