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PDF ML610Q112 Data sheet ( Hoja de datos )
| Número de pieza | ML610Q112 | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | LAPIS Semiconductor | |
| Logotipo |  |
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ML610Q111/ML610Q112
8-bit Microcontroller
FEDL610Q111-01
Issue Date: Sep. 26, 2013
GENERAL DESCRIPTION
This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as timers, PWM, UART, I2C
bus interface (master/slave), synchronous serial port, voltage level supervisor analog comparators and 10-bit successive
approximation type A/D converter, are incorporated around 8-bit CPU nX-U8/100.
The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by pipe line architecture parallel
processing. The Flash ROM that is installed as program memory, and the on-chip debug function that is installed, enable program
debugging and programming on customer’s board.
FEATURES
z CPU
− 8-bit RISC CPU (CPU name: nX-U8/100)
− Instruction system: 16-bit instructions
− Instruction set:
Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic
operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
− On-Chip debug function
− Minimum instruction execution time:
30.5us (@32.768kHz system clock)
0.122us (@8.192MHz system clock)
z Internal memory
− ML610Q111:
Flash memory :
Internal 24Kbyte Flash memory (12K x 16bit) for program including unusable 32byte test data area.
Internal 4Kbyte Flash memory (2K x 16bit) for data.
SRAM :
Internal 2Kbyte data RAM (2K x 8bit)
− ML610Q112:
Flash memory :
Internal 32Kbyte Flash memory (16K x 16bit) for program including unusable 32byte test data area.
Internal 4Kbyte Flash memory (2K x 16bit) for data.
SRAM :
Internal 4Kbyte data RAM (4K x 8bit)
− Flash Memory operating condition and specification
Refer to the chapter Electrical characteristics “FLASH MEMORY SPECIFIACTION”.
z Interrupt controller
− 1 non-maskable interrupt source (Internal source: 1(WDT))
− 30 maskable interrupt sources (Internal sources: 23, External source: 7)
z Time base counter (TBC)
− Low-speed time base counter: 1 channel
− High-speed time base counter: 1 channel
(This time base counter is divided by 1-16, then it can be used as a clock of the Timer and PWM.)
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1 page  
FEDL610Q111-01
ML610Q111/ML610Q112
BLOCK DIAGRAM
The block diagram is shown in figure 1.
“*” means secondary function, tertiary function or quaternary function of each port.
“( )*2” means the function of ML610Q112.
RESET_N
TEST
VDD
VSS
RESET_N
TEST
AIN0
to
AIN5(AIN7)*2
CMP0P
CMP0M
CMP0OUT*
CMP1P
CMP1OUT*
EPSW1 - 3
PSW
Timing
Controller
CPU (nX-U8/100)
GREG
0 - 15
ELR1 - 3
LR
EA
ALU
SP
On-Chip
ICE
Instruction
Decoder
Instruction
Register
Data-bus
Power
RESET &
TEST
Clock
Generator
VLS
INT
1
10bit-ADC
INT
1
Analog
Comparator
x2
INT
2
Data
Memory
(Flash)
4Kbyte
RAM
2Kbyte
(4Kbyte)*2
Interrupt
Controller
INT
1 WDT
INT
4 TBC
INT
6 8bit Timer
x6
ECSR1 - 3
DSR/CSR
PC
BUS
Controller
Program
Memory
(Flash)
24Kbyte
(32Kbyte)*2
INT
2
UART
INT
2 I2C
Master/Slave
INT
1
SSIO
INT
4
PWM
INT
7
GPIO
Figure 1. ML610Q111/ML610Q112 Block Diagram
RXD0
TXD0*
RXD1
TXD1*
SDA*
SCL*
SCK*
SIN*
SOUT*
PWMC*
PWMD*,
PWME*
PWMF0*
PWMF1*
PWMF2*
PA0 to PA2
PB0 to PB7
PC0 to PC3
(PC4 to PC7)*2
(PD0 to PD5)*2
5/26
5 Page 
FEDL610Q111-01
ML610Q111/ML610Q112
PWMF2
PWMF2 output pin. This pin is used as the tertiary function of the PC2 and also the Tertiary/
O quaternary function of the PB5 pin.
Quaternary
Pin name I/O
Description
Primary
Secondary
Tertiary,
Quaternary
External Interrupt
EXI0 to 2
External maskable interrupt input pins. Interrupt enable and edge selection can be
I performed for each bit by software. These pins are used as the primary functions of the
PA0 – PA2 pins.
Primary
EXI4 to 7
External maskable interrupt input pins. Interrupt enable and edge selection can be
I performed for each bit by software. These pins are used as the primary functions of the
PB0 – PB3 pins.
Primary
Timer
TETE, TFTG
External clock input pin used for both Timer E and Timer F.These pins are used as the
I Primary
primary function of the PA0-PA2, PB0-PB7 pins.
TM9OUT
O Timer 9 output pin. This pin is used as the quaternary function of the PA0 and PC0 pin. Quaternary
TMFOUT
O Timer F output pin. This pin is used as the quaternary function of the PA1 and PC3 pin. Quaternary
Successive approximation type A/D converter
AIN0
I Channel 0 analog input for successive approximation type A/D converter. This pin is
used as the primary function of the PA0 pin.
Primary
AIN1
I Channel 1 analog input for successive approximation type A/D converter. This pin is Primary
used as the primary function of the PA1 pin.
AIN2
I Channel 2 analog input for successive approximation type A/D converter. This pin is
Primary
used as the primary function of the PB0 pin.
AIN3
I Channel 3 analog input for successive approximation type A/D converter. This pin is
used as the primary function of the PB1 pin.
Primary
AIN4
I Channel 4 analog input for successive approximation type A/D converter. This pin is
Primary
used as the primary function of the PB6 pin.
AIN5
I Channel 5 analog input for successive approximation type A/D converter. This pin is
used as the primary function of the PB7 pin.
Primary
AIN6
I Channel 6 analog input for successive approximation type A/D converter. This pin is Primary
used as the primary function of the PC6 pin.
AIN7
I Channel 7 analog input for successive approximation type A/D converter. This pin is
used as the primary function of the PC7 pin.
Primary
Comparator
CMP0P
CMP0M
CMP0OUT
CMP1P
CMP1OUT
TEST
I Non-inverting input for comparator0. This pin is used as the primary function of the PB4 Primary
pin.
I Inverting input for comparator0. This pin is used as the primary function of the PB5 pin. Primary
O Output for comparator0. This pin is used as the quaternary function of the PA2 pin.
Quaternary
I Non-inverting input for comparator1. This pin is used as the primary function of the PA1
pin. Primary
O Output for comparator1. This pin is used as the quaternary function of the PB0 pin.
Quaternary
TEST
TESTF
Power Supply
VSS
VDD
I/O Input/output pin for testing. A pull-down resistor is internally connected.
— Test pin for flash memory. A pull-down resistor is internally connected.
— Negative power supply pin.
— Positive power supply pin.
—
—
—
—
Positive/
Negative
Logic
Positive/
negative
Positive/
negative
—
Positive
Positive
—
—
—
—
—
—
—
—
—
—
—
—
—
Positive
—
—
—
11/26
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet ML610Q112.PDF ] | |
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