PDF ML610347 Data sheet ( Hoja de datos )

Número de pieza	ML610347
Descripción	8-bit Microcontroller
Fabricantes	LAPIS Semiconductor
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No Preview Available ! ML610Q347/ML610347 8-bit Microcontroller with Voice Output Function FEDL610Q347FULL-01 Issue Date: January 7, 2010 GENERAL DESCRIPTION Equipped with an LAPIS Semiconductor original 8-bit CPU nX-U8/100, the ML610Q347/ML610347 is a high-performance 8-bit CMOS microcontroller that integrates a wide variety of peripherals such as an 12-bit A/D converter, timer, synchronous serial port, UART, and voice output function. The nX-U8/100 CPU is capable of executing instructions efficiently on a one-instruction-per-clock-pulse basis through parallel processing by the 3-stage pipelined architecture. The microcontroller is also equipped with a flash memory that has achieved low voltage and low power consumption (at read) equivalent to mask ROMs, so it is best suited to battery-driven applications such as cellular phones. In addition, it has an on-chip debugging function, which allows software debugging/rewriting with the LSI mounted on the board. FEATURES  CPU  8-bit RISC CPU (CPU name: nX-U8/100)  Instruction repertoire: 16-bit length instructions  Instruction set: Transfer, arithmetic operations, comparison, logical operations, multiply/divide operations, bit manipulation, bit logical operations, jump, conditional jump, call return stack manipulation, and arithmetic shift instructions.  Built-in on-chip debugging function  Minimum instruction execution time: 31.25 s (@ 32kHz system clock) 0.244 s (@ 4.096 MHz system clock)  Internal memory  ML610Q347 Has 128-Kbyte flash memory (64K  16-bit) built in. (including unusable 1KByte TEST area)  ML610347 Has 128-Kbyte mask memory (64K  16-bit) built in. (including unusable 1KByte TEST area)  Has 1-Kbyte RAM (1024  8-bit) built in.  Interrupt controller  Non-maskable interrupt: 2 sources (1 internal source and 1 external sources)  Maskable interrupt: 18 sources (10 internal sources and 8 external sources)  Time-base counter  Low-speed side time-base counter  1ch  High-speed side time-base counter  1ch  Watchdog timer  Generates a non-maskable interrupt upon the first overflow and a system reset occurs upon the second  Free-running  Selectable overflow period: 4 types (125 ms, 500 ms, 2 sec, 8 sec)  Timer  8-bit  2ch (16-bit configuration also enabled) 1/29 1 page FEDL610Q347FULL-01 ML610Q347/347 Figure 2 is a block diagram of the ML610347. Symbols with an asterisk “” indicate that each of them is the secondary or tertiary function of the corresponding port. CPU (nX-U8/100) EPSW1～3 PSW GREG 0～15 ELR1～3 LR ECSR1～3 DSR/CSR Timing Controller On-Chip ICE ALU Instruction Decoder EA SP Instruction Register PC BUS Controller Program Memory （Mask） 128Kbyte VDD VSS RESET_N TEST OSC0 OSC1 LSCLK OUTCLK* RESET & TEST OSC RC32K VVDDDDLL SPVDD SPVSS SG SPP SPM AOUT SPIN AVDD AVSS VREF AIN0 to AIN11 POWER VOICECNT INT 1 12bit-ADC INT 1 Data-bus RAM 1024byte Interrupt Controller INT 4 TBC INT 2 8bit Timer ×2 INT WDT INT 1 SSIO INT 1 UART INT 9 GPIO SCK01 SIN01 SOUT01 RXD01 TXD01 NMI P00 to P07 P20 to P23 P30 to P37 P40 to P47 Figure 2 Block Diagram of ML610347 5/29 5 Page FEDL610Q347FULL-01 ML610Q347/347 PIN DESCRIPTION Pin name I/O Description Power supply VSS VDD VDDL SPVSS SPVDD AVSS AVDD VPP() Test — Negative power supply pin — Positive power supply pin — Positive power supply pin for internal logic (internally generated) Capacitors CL(see measuring circuit 1) are connected between this pin and VSS. — Negative power supply pin for built-in speaker amplifier — Positive power supply pin for built-in speaker amplifier — Negative power supply pin for successive-approximation type ADC — Positive power supply pin for successive-approximation type ADC — Power supply pin for flash memory TEST I/O Input/output pin for testing. Has a pull-down resistor built in. System RESET_N I Reset input pin. When this pin is set to a “L” level, the device is placed in system reset mode and the internal circuit is initialized. If after that this pin is set to a “H” level, program execution starts. This pin has a pull-up resistor built in. OSC0 OSC1 LSCLK I Pins for connecting a crystal unit for high speed clock. O Connect a 4.096 MHz crystal unit (see Measuring Circuit 1) to these pins. Also, connect capacitors (CDH and CGH) between these pins and VSS as required. O Low-speed clock output. This function is allocated to the secondary function of the P20 and P36 pins. OUTCLK O High-speed clock output. This function is allocated to the secondary function of the P21 and P37 pins. General-purpose Input port P00–P07 I General-purpose input ports. Primary/ Secondary/ Tertiary — — — — — — — — — — — — Secondary Secondary Primary General-purpose Output port P20–P23 O General-purpose output ports. Provided with a secondary function. Cannot be used as ports if their secondary function is used. General-purpose Input/output port P30–P37 P40–P47 I/O General-purpose input/output ports. I/O Provided with a secondary function. Cannot be used as ports if their secondary function is used. Primary Primary Logic — — — — — — — — Positive Negative — — — — Positive Positive Positive *Applies to the ML610Q347. 11/29 11 Page

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