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87332I-01 の電気的特性と機能

87332I-01のメーカーはIDTです、この部品の機能は「ECL/LVPECL Clock Generator」です。


製品の詳細 ( Datasheet PDF )

部品番号 87332I-01
部品説明 ECL/LVPECL Clock Generator
メーカ IDT
ロゴ IDT ロゴ 




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87332I-01 Datasheet, 87332I-01 PDF,ピン配置, 機能
÷2, Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator
87332I-01
DATA SHEET
GENERAL DESCRIPTION
The 87332I-01 is a high performance ÷2 Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator. The CLK, nCLK pair can accept
most standard differential input levels The 87332I-01 is characterized
to operate from either a 2.5V or a 3.3V power supply. Guaranteed
output and part-to-part skew characteristics make the 87332I-01
ideal for those clock distribution applications demanding well defined
performance and repeatability.
FEATURES
• One ÷2 differential 2.5V/3.3V LVPECL / ECL output
• One CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency: 500MHz
• Maximum input frequency: 1GHz
• Translates any single ended input signal to 3.3V LVPECL
levels with resistor bias on nCLK input
• Part-to-part skew: 400ps (maximum)
• Propagation delay: 1.6ns (maximum)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -2.375V to -3.8V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
BLOCK DIAGRAM
CLK
nCLK
÷2
Q
nQ
MR
PIN ASSIGNMENT
MR
CLK
nCLK
nc
1
2
3
4
8 Vcc
7Q
6 nQ
5 VEE
87332I-01
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
87332AMI-01 REVISION C 2/12/15
1 ©2015 Integrated Device Technology, Inc.

1 Page





87332I-01 pdf, ピン配列
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC
Inputs, VI
Outputs, IO
Continuous Current
Surge Current
4.6V
-0.5V to VCC + 0.5 V
50mA
100mA
Package Thermal Impedance, θJA 112.7°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
87332AMI-01 DATA SHEET
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40°C TO 85°C
Symbol
VCC
IEE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
3.3
Maximum
3.8
30
Units
V
mA
TABLE 3B. LVCMOS DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40°C TO 85°C
Symbol
VIH
VIL
IIH
IIL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
MR
MR
MR
MR
Test Conditions
VCC = VIN = 3.8V
VCC = 3.8V, VIN = 0V
Minimum
2
-0.3
Typical
-5
Maximum
VCC + 0.3
0.8
150
Units
V
V
µA
µA
TABLE 3C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
IIH
IIL
VPP
V
CMR
CLK
Input High Current
nCLK
CLK
Input Low Current
nCLK
Peak-to-Peak Input Voltage
Common Mode Input Voltage;
NOTE 1, 2
VCC = VIN = 3.8V
VCC = VIN = 3.8V
VCC = 3.8V, VIN = 0V
VCC = 3.8V, VIN = 0V
-5
-150
0.15
V + 0.5
EE
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
Maximum
150
5
1.3
Units
µA
µA
µA
µA
V
V - 0.85
CC
V
REVISION C 2/12/15
3 ÷2, Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator


3Pages


87332I-01 電子部品, 半導体
87332AMI-01 DATA SHEET
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single need to be adjusted to position the V_REF in the center of the input
ended levels. The reference voltage V_REF = VCC/2 is generated by
the bias resistors R1, R2 and C1. This bias circuit should be located
as close as possible to the input pin. The ratio of R1 and R2 might
voltage swing. For example, if the input clock swing is only 2.5V and
VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
Single Ended Clock Input
V_REF
C1
0.1u
R1
1K
CLK
nCLK
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 3A and 3B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
3.3V
3.3V
R3 R4
125
125
3.3V
Zo = 50
+
Zo = 50
R1
84
_
R2
84
Input
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
÷2, Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator
6
REVISION C 2/12/15

6 Page



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部品番号部品説明メーカ
87332I-01

ECL/LVPECL Clock Generator

IDT
IDT


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