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PDF STV7697 Data sheet ( Hoja de datos )
| Número de pieza | STV7697 | |
| Descripción | PLASMA DISPLAY PANEL SCAN DRIVER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de STV7697 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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STV7697
PLASMA DISPLAY PANEL SCAN DRIVER
.......... 64 OUTPUTS PLASMADISPLAY DRIVER
170V ABSOLUTE MAXIMUM SUPPLY
5V SUPPLY FOR LOGIC
40/200mA SOURCE / SINK OUTPUT
400mA SOURCE / SINK OUTPUT DIODE
64-BIT SHIFT REGISTER (20MHz)
BLANK CONTROL
COMPLEMENTARY OUTPUT CONTROL
BCD TECHNOLOGY
100 PINS PQFP PACKAGE OR DICE
PRODUCT PREVIEW
DESCRIPTION
The STV7697 is a scan driver for Plasma Display
Panel (PDP) implemented in SGS-THOMSON’s
proprietary BCD technology.Using a 64-bit cascad-
able 20MHz shift register, it drives 64 high current &
high voltage outputs. By serialy connecting several
STV7697, any vertical pixel definition can be per-
formed. The STV7697 is supplied with a separated
160V power output supply and a 5V logic supply.
PIN CONNECTIONS
PQFP100 (14 x 20 x 2.80mm
(Full Plastic Quad Flat Pack)
ORDER CODE : STV7697
All command inputs are CMOS compatible. The
STV7697 package is a 100 pins PQFP.
OUT34
OUT33
VPP
VSSP
VSSP
VSSP
VPP
VSSSUB
VSSLOG
VSSLOG
VCC
VSSLOG
VSSSUB
VPP
VSSP
VSSP
VSSP
VPP
OUT32
OUT31
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
STV7697
PQFP100
100
99
98
97
96
VPP
VSSP
VSSP
VPP
NC
95 NC
94 VSSLOG
93 CLK
92 STB
91 SOUT(SIN)
90 VCC
89 SIN(SOUT)
88 NC
87 F/R
86 BLK
85 POL
84 VPP
83 VSSP
82 VSSP
81 VPP
June 1998
This is advance information on a new product now in development or undergoing evaluatio n. Details are subject to change without notice.
1/8
1 page  
STV7697
AC TIMINGS REQUIREMENTS
(VCC = 4.5V to 5.5V, Tamb = -20 to +85°C, input signals max leading edge & trailing edge (tR, tF) = 10ns)
Symbol
Parameter
Min. Typ. Max. Unit
tCLK Data Clock Period
50 -
- ns
tWHCLK Duration of clock (CLK) pulse at high level
15 -
- ns
tWLCLK Duration of clock (CLK) pulse at low level
15 -
- ns
tSDAT
tHDAT
Set-up Time of data input before clock low to high transition
Hold Time of data input after clock low to high transition
10 -
10 -
- ns
- ns
tSFR Forward/Reverse(F/R) set up time before low to high clock transition 100
-
- ns
tDSTB
Minimum Delay to latch (STB) after clock low to high transition
10 -
- ns
tSTB Strobe (STB) Pulse Duration
20 -
- ns
tBLK Blank (BLK) Pulse Duration
500 -
- ns
tPOL Polarity (POL) Pulse Duration
500 -
- ns
AC TIMING CHARACTERISTICS
(VCC = 5V, VPP = 130V, VSSP = 0V, VSSLOG = VSSSUB = 0V, Tamb = 25°C, fCLK = 20MHz, VILMax. = 0.2VCC,
VIHMin. = 0.8VCC, VOH = 4.0V, VOL = 0.4V, CL = 15pF, unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Unit
tCLK
tRDAT
tFDAT
Data Clock Period
Logical Data Output Rise Time
Logical Data Output Fall Time
50 -
- ns
- 20 - ns
- 11 - ns
tPHL1 Delay of logic data output after clock (CLK) high to low transition
tPLH1 Delay of logic data output after clock (CLK) low to high transition
- 45 - ns
- 48 - ns
tPHL2 Delay of power output change after clock (CLK) high to low transition
tPLH2 Delay of power output change after clock (CLK) low to high transition
-
120 180
ns
-
120 180
ns
tPHL3 Delay of power output change after blanking (BLK) high to low transition
tPLH3 Delay of power output change after blanking (BLK) low to high transition
-
-
110 165
110 165
ns
ns
tPHL4 Delay of power output change after polarity (POL) high to low transition
tPLH4 Delay of power output change after polarity (POL) low to high transition
-
-
- 160 ns
- 160 ns
tROUT Power Output Rise Time (6)
tFOUT Power Output Fall Time (6)
-
100 200
ns
- 60 200 ns
Notes : 6. One output among 64, loading capacitor COUT = 100pF, other outputs at low level.
5/8
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet STV7697.PDF ] | |
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