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HEF4016BのメーカーはPhilipsです、この部品の機能は「Quadruple bilateral switches」です。 |
部品番号 | HEF4016B |
| |
部品説明 | Quadruple bilateral switches | ||
メーカ | Philips | ||
ロゴ | |||
このページの下部にプレビューとHEF4016Bダウンロード(pdfファイル)リンクがあります。 Total 8 pages
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4016B
gates
Quadruple bilateral switches
Product specification
File under Integrated Circuits, IC04
January 1995
1 Page Philips Semiconductors
Quadruple bilateral switches
Product specification
HEF4016B
gates
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Power dissipation per switch
P
For other RATINGS see Family Specifications
max.
100 mW
DC CHARACTERISTICS
Tamb = 25 °C; VSS = 0 V (unless otherwise specified)
PARAMETER
VDD
V
SYMBOL TYP.
ON resistance
ON resistance
ON resistance
‘∆’ ON resistance
between any two
channels
5
10 RON
15
5
10 RON
15
5
10 RON
15
5
10 ∆RON
15
8000
230
115
140
65
50
170
95
75
200
15
10
MAX.
−
690
350
425
195
145
515
285
220
−
−
−
UNIT
CONDITIONS
Ω En at VIH; Vis = 0 to VDD; see Fig.4
Ω
Ω
Ω En at VIH; Vis = VSS; see Fig.4
Ω
Ω
Ω En at VIH; Vis = VDD; see Fig.4
Ω
Ω
Ω En at VIH; Vis = 0 to VDD; see Fig.4
Ω
Ω
PARAMETER
Quiescent
device
current
Input leakage
current at En
OFF-state leakage
current, any
channel OFF
En input
voltage LOW
En input
voltage HIGH
VDD
V SYMBOL
−40
Tamb (°C)
+ 25
+ 85 UNIT
CONDITION
MIN. MAX. MIN. MAX. MIN. MAX.
5
10 IDD
15
15 ± IIN
− 1,0 − 1,0 − 7,5 µA VSS = 0; all valid
− 2,0 − 2,0 − 15,0 µA input combinations;
− 4,0 − 4,0 − 30,0 µA VI = VSS or VDD
− − − 300 − 1000
nA En at VSS or VDD
5
10 IOZ
15
5
10 VIL
15
5
10 VIH
15
− − − − − − nA
− − − − − − nA
− − − 200 − − nA
− 1,5 − 1,5 − 1,5 V
− 3,0 − 3,0 − 3,0 V
− 4,0 − 4,0 − 4,0 V
3,5 − 3,5 − 3,5 − V
7,0 − 7,0 − 7,0 − V
11,0 − 11,0 − 11,0 − V
En at VIL;
Vis = VSS or VDD;
Vos = VDD or VSS
switch OFF; see
Fig.9 for IOZ
low-impedance
between Y and Z (ON
condition)
see RON switch
January 1995
3
3Pages Philips Semiconductors
Quadruple bilateral switches
Product specification
HEF4016B
gates
Notes
Vis is the input voltage at a Y or Z terminal, whichever is assigned as input.
Vos is the output voltage at a Y or Z terminal, whichever is assigned as output.
1. RL = 10 kΩ to VSS; CL = 50 pF to VSS; En = VDD; Vis = VDD (square-wave); see Figs 6 and 10.
2. RL = 10 kΩ; CL = 50 pF to VSS; En = VDD (square-wave);
Vis = VDD and RL to VSS for tPHZ and tPZH;
Vis = VSS and RL to VDD for tPLZ and tPZL; see Figs 6 and 11.
3. RL = 10 kΩ; CL = 15 pF; En = VDD; Vis = 1⁄2VDD(p-p) (sine-wave, symmetrical about 1⁄2VDD);
fis = 1 kHz; see Fig.7.
4. RL = 1 kΩ; Vis = 1⁄2VDD(p-p) (sine-wave, symmetrical about 1⁄2VDD);
20 log V-V----o-i-s-s---(-(-A-B---)-)= –50 dB; En (A)= VSS; En (B) = VDD; see Fig. 8.
5. RL = 10 kΩ to VSS; CL = 15 pF to VSS; En = VDD (square-wave); crosstalk is Vos (peak value);
see Fig.6.
6. RL = 1 kΩ; CL = 5 pF; En = VSS; Vis = 1⁄2VDD(p-p) (sine-wave, symmetrical about 1⁄2VDD);
20 log -VV----oi--s-s= –50 dB; see Fig. 7.
7. RL = 1 kΩ; CL = 5 pF; En = VDD; Vis = 1⁄2VDD(p-p) (sine-wave, symmetrical about 1⁄2VDD);
20 log -VV----o-i-s-s = –3 dB; see Fig. 7.
Dynamic power
dissipation per
package (P)(1)
VDD
V
5
10
15
Note
1. All enable inputs switching.
TYPICAL FORMULA FOR P (µW)
550 fi + ∑ (foCL) × VDD2
2 600 fi + ∑ (foCL) × VDD2
6 500 fi + ∑ (foCL) × VDD2
where
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
6
6 Page | |||
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