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ST20C2 の電気的特性と機能

ST20C2のメーカーはSTMicroelectronicsです、この部品の機能は「Instruction Set Reference Manual」です。


製品の詳細 ( Datasheet PDF )

部品番号 ST20C2
部品説明 Instruction Set Reference Manual
メーカ STMicroelectronics
ロゴ STMicroelectronics ロゴ 




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Total 30 pages

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ST20C2 Datasheet, ST20C2 PDF,ピン配置, 機能
ST20C2/C4 Core
Instruction Set
Reference Manual
72-TRN-273-01 January 1996
®

1 Page





ST20C2 pdf, ピン配列
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.1 Instruction name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.2 Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.4 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.5 Error signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.6 Comments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.7 Notation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.7.1
1.7.2
1.7.3
1.7.4
1.7.5
1.7.6
The processor state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Undefined values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Representing memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.8 Block move registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.9 Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.10 Operators used in the definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.11 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.12 Conditions to instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2 Addressing and data representation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.1 Word address and byte selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.2 Ordering of information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.3 Signed integers and sign extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.1 Machine registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.1.1 Process state registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.1.2 Other machine registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.2 The process descriptor and its associated register fields . . . . . . . . . . . . . 24
4 Instruction representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.1 Instruction encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
An instruction component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
The instruction data value and prefixing . . . . . . . . . . . . . . . . . . .25
Primary Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Secondary instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Summary of encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.2 Generating prefix sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.2.1 Prefixing a constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.2.2 Evaluating minimal symbol offsets . . . . . . . . . . . . . . . . . . . . . . . .29
5 Instruction Set Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3/212
®


3Pages


ST20C2 電子部品, 半導体
1.3 Description
The description section provides an indication of the purpose of the instruction as well
as a summary of the behavior. This includes details of the use of registers, whose
initial values may be used as parameters and into which results may be stored.
Example
The add instruction contains the following description:
Description: Add Areg and Breg, with checking for overflow.
1.4 Definition
The definition section provides a formal description of the behavior of the instruction.
The behavior is defined in ter ms of its effect on the state of the processor (i.e. the
values in registers and memory before and after the instruction has executed).
The effects of the instruction on registers, etc. are given as relationships of the
following form:
register′ ← expression involving registers, etc.
Primed names (e.g. Areg) represent values after instruction execution, while
unprimed names represent values when instruction execution starts. For example,
Areg represents the value in Areg before the execution of the instruction while Areg
represents the value in Areg afterwards. So, the example above states that the
register on the left hand side becomes equal to the value of the expression on the
right hand side after the instruction has been executed.
The description is written with the main function of the instruction stated first (e .g. the
main function of the add instruction is to put the sum of Areg and Breg into Areg).
This is followed by the other effects of the instruction (e.g. popping the stack). There is
no temporal ordering implied by the order in which the statements are written.
The notation is described more fully in section 1.7.
Example
The add instruction contains the following description:
Definition:
Areg′ ← Breg + checked Areg
Breg′ ← Creg
Creg′ ← undefined
This says that the integer stack is popped and Areg assigned the sum of the values
that were initially in Breg and Areg. After the instruction has executed Breg contains
the value that was originally in Creg, and Creg is undefined.
6/212
®

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
ST20C2

Instruction Set Reference Manual

STMicroelectronics
STMicroelectronics
ST20C4

Instruction Set Reference Manual

STMicroelectronics
STMicroelectronics
ST20Cx

Instruction Set Reference Manual

ST Microelectronics
ST Microelectronics


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