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PDF HCPL-7840 Data sheet ( Hoja de datos )
| Número de pieza | HCPL-7840 | |
| Descripción | Isolation Amplifier | |
| Fabricantes | Avago | |
| Logotipo |  |
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HCPL-7840
Isolation Amplifier
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
The HCPL-7840 isolation amplifier family was designed
for current sensing in electronic motor drives. In a typical
implementation, motor currents flow through an external
resistor and the resulting analog voltage drop is sensed by
the HCPL-7840. A differential output voltage is created on
the other side of the HCPL-7840 optical isolation barrier.
This differential output voltage is proportional to the
motor current and can be converted to a single-ended
signal by using an op-amp as shown in the recommended
application circuit. Since common-mode voltage swings
of several hundred volts in tens of nanoseconds are
common in modern switching inverter motor drives, the
HCPL-7840 was designed to ignore very high common-
mode transient slew rates (of at least 10 kV/μs).
The high CMR capability of the HCPL-7840 isolation
amplifier provides the precision and stability needed to
accurately monitor motor current in high noise motor
control environ-ments, providing for smoother control
(less “torque ripple”) in various types of motor control
applications.
The product can also be used for general analog signal
isolation applications requiring high accuracy, stability,
and linearity under similarly severe noise con-ditions. For
general applications, we recommend the HCPL-7840 (gain
tolerance of ± 5%). The HCPL-7840 utilizes sigma delta
(∑-Δ) analog-to-digital converter technology, chopper
stabilized amplifiers, and a fully differential circuit topol-
ogy fabricated using Avago’s 0.8 μm CMOS IC process.
Together, these features deliver unequaled isolation-
mode noise rejection, as well as excellent offset and gain
accuracy and stability over time and temperature. This
performance is delivered in a compact, auto-insertable,
industry standard 8-pin DIP package that meets world-
wide regulatory safety standards. (A gull-wing surface
mount option #300 is also available).
Features
15 kV/μs common-mode rejection at V = 1000 V
CM
Compact, auto-insertable standard 8-pin DIP package
0.00025 V/V/°C gain drift vs. temperature
0.3 mV input offset voltage
100 kHz bandwidth
0.004% nonlinearity
Worldwide safety approval:
UL 1577 (3750 Vrms/1 min.)
and CSA, IEC/EN/DIN EN 60747-5-2
Advanced Sigma-Delta (∑-Δ) A/D converter technol-
ogy
Fully differential circuit topology
0.8 μm CMOS IC technology
Applications
Motor phase and rail current sensing
Inverter current sensing
Switched mode power supply signal isolation
General purpose current sensing and monitoring
General purpose analog signal isolation
Functional Diagram
IDD1
VDD1 1
IDD2
8 VDD2
VIN+ 2
+
+ 7 VOUT+
VIN– 3
–
– 6 VOUT–
GND1 4
SHIELD
5 GND2
A 0.1 μF bypass capacitor must be connected
between pins 1 and 4 and between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
1 page  
Solder Reflow Temperature Profile
300
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC. PEAK
TEMP.
245°C
200
160°C
150°C
140°C
100
2.5°C ± 0.5°C/SEC.
3°C + 1°C/–0.5°C
PREHEATING TIME
150°C, 90 + 30 SEC.
30
SEC.
30
SEC.
PEAK
TEMP.
240°C
PEAK
TEMP.
230°C
SOLDERING
TIME
200°C
50 SEC.
ROOM
TEMPERATURE
0
0
TIGHT
TYPICAL
LOOSE
50 100 150 200 250
TIME (SECONDS)
Note: Non-halide flux should be used..
Recommended Pb-Free IR Profile
Tp 260 +0/-5 °C
TL 217 °C
RAMP-UP
3 °C/SEC. MAX.
Tsmax 150 - 200 °C
Tsmin
ts
PREHEAT
60 to 180 SEC.
tp
tL
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
20-40 SEC.
RAMP-DOWN
6 °C/SEC. MAX.
60 to 150 SEC.
25
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C
Note: Non-halide flux should be used.
5
5 Page 
VDD1
0.1 µF
VDD2
18
0.1 µF
2 7 10 K
HCPL-7840
36
10 K
4 5 0.47
µF
+15 V
0.1 µF
+
– AD624CD
GAIN = 100
0.47
µF
0.1 µF
VOUT
-15 V
Figure 1. Input offset voltage test circuit.
0.8 0.39
vs. VDD1
0.7 0.38
vs. VDD2
0.6 0.37
0.5 0.36
0.4 0.35
0.3
0.2
-55
-25 5 35 65 95
TA – TEMPERATURE – °C
125
Figure 2. Input offset voltage vs. temperature.
0.34
0.33
4.5
4.75 5.0 5.25
VDD – SUPPLY VOLTAGE – V
Figure 3. Input offset vs. supply.
5.5
8.035
8.03
8.025
8.02
8.015
8.01
-55 -35 -15 5 25 45 65 85 105 125
TA – TEMPERATURE – °C
Figure 4. Gain vs. temperature.
VDD1
404
VIN
0.1 µF
13.2
0.01 µF
1
2
3
4
HCPL-7840
VDD2
8
0.1 µF
7 10 K
6 10 K
5 0.47
µF
Figure 5. Gain and nonlinearity test circuit.
+15 V
0.1 µF
+15 V
0.1 µF
+
– AD624CD
GAIN = 4
0.47 0.1 µF
µF
-15 V
10 K
0.47
µF
+
– AD624CD
GAIN = 10
VOUT
0.1 µF
-15 V
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet HCPL-7840.PDF ] | |
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