DataSheet.jp

ISL58315 の電気的特性と機能

ISL58315のメーカーはIntersil Corporationです、この部品の機能は「High Speed Triple Laser Diode Drivers」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL58315
部品説明 High Speed Triple Laser Diode Drivers
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




このページの下部にプレビューとISL58315ダウンロード(pdfファイル)リンクがあります。

Total 30 pages

No Preview Available !

ISL58315 Datasheet, ISL58315 PDF,ピン配置, 機能
High Speed Triple Laser Diode Drivers
ISL58315
The ISL58315 is a high-speed, triple-output laser diode driver
(LDD) for laser scanning projector systems, which require three
channels modulated at high speed with independent current
control.
Features
• High-speed, triple-output laser diode driver supporting up to
720-pixel HD resolution
Each output channel provides laser-independent current
• Up to 1A of peak current output
control for threshold and color DACs. Separate scale DACs
allow independent scaling of both threshold and color DAC
output values. This allows control of projector brightness and
can be used to simplify automatic power calibration (APC) for
• Fast output switching speeds with pulse rise/fall times of
1ns to 2ns for crisp pixels
• Intersil patented laser voltage sampler function provides
laser-based systems.
dynamic power management capability to dramatically
Pixel data information is transferred through the LDD's
minimize system power
high-speed 10-bit or 15-bit parallel video interface. Three
parallel interface modes provide flexibility and allow users a
trade-off among speed, power and bus width. Pixel data
employs a double data rate scheme, allowing video data to be
C O N F I D E N T I A Ltransferred using both clock edges.
• Intersil patented SmartLinearizer™ DAC feature provides a
linear transfer function (input video code to green laser
output), eliminating the need for DSP controller processing
algorithms required for non-linear green lasers
• Flexible 10-bit or Intersil patented 15-bit RGB pixel input
Applications
formats supported to reduce speed and power. 300MHz
• Laser-based Pico Projectors
• RGB Scanning and Field-based laser projection systems
maximum data Input rate supported for 10-bit RGB mode
• Blanking time power reduction reduces LDD current
consumption to 3mA typical
• Generic laser-based applications requiring multiple,
independently controlled lasers
• Programmable return-to-zero (RTZ) function provides
maximum flexibility
Related Literature
• See application block diagram for Pico Projector (MEMS) at:
http://www.intersil.com/applications/PicoProjector%28MEMS%29.asp
• Integrated heater function for SHG green lasers reduces
external components
• Single 3.3V supply and 1.8V video interface compatible for
low power
SEN
SCLK
SD IO
D [14..0]*
CLK
LO W P
RTZ
CE
S E R IA L
IN T E R F A C E
DATA
IN T E R F A C E
AND
R EG ISTER S
HEATER
ADC
GLUE
LO G IC
OUTPUT
CHANNEL 3
OUTPUT
CHANNEL 2
OUTPUT
CHANNEL 1
MON
IOUT3
NC
IOUT2
IOUT1
NOTE:
* TH E FO LLO W IN G D A TA LIN ES H A VE A LTER N A TIVE U SE, D EPEN D IN G O N
REG ISTER SETTING : D2 = EN3, D4 = EN 2, D 6 = EN1, AN D D10 = SYNC
FIGURE 1. BLOCK DIAGRAM
September 30, 2011
FN7543.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) and SmartLinearizer are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL58315 pdf, ピン配列
ISL58315
Pin Descriptions
PIN
NAME
PIN #
PIN
TYPE
PIN DESCRIPTION
CE 22 Digital CE is an input 3.3V logic signal. When high, it enables the device. Other enables are in the registers.
LOWP 37 Digital LOWP is a 3.3V signal. When LOWP is asserted (high), the device goes into low-power mode.
RTZ 39 Digital RTZ signal can be operated with 1.8V or 3.3V. The operating voltage is selected via Reg 0x08
Bits 6 and 7. By default, it is 1.8V. This is a high-speed signal.
D14 to D0
15, 14, 13, 12, 10,
9, 8, 6, 4, 2, 1
(Pins 11, 7, 5, 3
described
separately)
Digital
These 15 pins form the Input Pixel Data bus. RGB data enters this bus to drive the laser output
channels. See “Functional Description” on page 11 for specific data formats.
These signals can be either 1.8V or 3.3V CMOS logic. The operating voltage is selected via Reg 0x08
Bit 6 and 7. By default, it is 1.8V.
NOTE: D2, D4, D6 and D10 have alternate functions depending on DATA CONTROL REGISTER -
ADDRESS 0x08 Bits 2-0. See description for pins EN1, EN2, EN3 and Sync.
SYNC/D10
11
Digital Sync signal is shared with D10. Sync has an effect only if input data bus mode 2 is selected.
CONFIDENTIALD2/EN3
3
Digital
This signal can be operated at 1.8V or 3.3V. The operating voltage is selected via Reg 0x08 Bit 6
and 7. By default, it is 1.8V.
This signal is available only when the LDD is programmed to use Mode 3 pixel input data format.
This signal is shared with D2.
EN3 is the output Channel 3 enable signal that allows an external ASIC direct control of enable. It
is intended for use with field sequential applications.
This signal can be operated at 1.8V or 3.3V. The operating voltage is selected via Reg 0x08 Bit 6
and7. By default, it is 1.8V.
D4/EN2
5
Digital
This signal is available only when the LDD is programmed to use Mode 3 pixel input data format.
This signal is shared with D4.
EN2 is the output Channel 2 enable signal that allows an external ASIC direct control of enable. It
is intended for use with field sequential applications.
This signal can be operated at 1.8V or 3.3V. The operating voltage is selected via Reg 0x08 Bit 6
and 7. By default, it is 1.8V.
D6/EN1
7
Digital
This signal is available only when the LDD is programmed to use Mode 3 pixel input data format.
This signal is shared with D6.
EN1 is the output Channel 1 enable signal that allows an external ASIC direct control of enable. It
is intended for use with field sequential applications.
This signal can be operated at 1.8V or 3.3V. The operating voltage is selected via Reg 0x08 Bit 6
and 7. By default, it is 1.8V.
CLK 40 Digital CLK is the input pixel clock. It is used to latch each IOUT channel’s pixel amplitude data. Both clock
edges are used. Nominal duty cycle should be 50%. For specific operating modes, see “Input Pixel
Data Interface” on page 11.
The clock signal can be operated at 1.8V or 3.3V. The operating voltage is selected via Reg 0x08
Bit 6 and 7. By default, it is 1.8V.
SEN 19 Digital SEN is a 3.3V signal. It is the SPI enable.
SCLK
18 Digital SCLK is a 3.3V signal. It is the SPI data clock.
SDIO
17 Digital SDIO is a 3.3V signal. It is the SPI bi-directional serial data.
IOUT1
24 Analog Current output for the IOUT1 laser. Current is sunk from the laser cathode to ground. IOUT1 and IOUT3
have similar performance capability.
IOUT3
29 Analog Current output for the IOUT3 laser. Current is sunk from the laser cathode to ground. IOUT1 and IOUT3
have similar performance capability.
IOUT2
RSET
26 Analog Current output for the IOUT2 laser. IOUT2 can sink high current; up to 1000mA peak.
32 Reference RSET pin allows for an external resistor to analog ground that sets the chip bias current level. All
other chip reference currents are derived from RSET. A typical resistance is 10kwith 1% tolerance,
and it should be placed as close to the pin as possible.
VDD
20, 21
Power Power supply pins for the device (can be applied after VDDA or at the same time). Typical 3.3V.
Independent de-coupling capacitors should be tied to each of these pins (Note 1).
3 FN7543.0
September 30, 2011


3Pages


ISL58315 電子部品, 半導体
ISL58315
Absolute Maximum Ratings TA = +25°C
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0V
Voltage at IOUT1, IOUT3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9.5V
Voltage at IOUT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.6V
Peak Output Current, IOUT1, IOUT3 . . . . . . . . . . . . . . . . . . . . . . . . . . 1000mA
Peak Output Current, IOUT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000mA
Logic Input Voltages . . . . -0.3V to VDD +0.3Vor 4.0V which ever is smaller
Current into RSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
ESD Rating
Human Body Model (per JESD22-A114-F) . . . . . . . . . . . . . . . . . . . 5000V
Machine Model (per JESD22-A115-C) . . . . . . . . . . . . . . . . . . . . . . . . 250V
Charged Device Model (per JESD22-C110-D) . . . . . . . . . . . . . . . . . 2000V
Latch Up (Tested per JESD-78; Class II, Level A). . . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
40 Ld TQFN (Notes 6, 7) . . . . . . . . . . . . . . . 28.5
0.9
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +85°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-60°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . -0°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
7. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
CONFIDENTIALIMPORTANT NOTE: Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed
tests; therefore, TJ = TC = TA.
DC Electrical Specifications Unless otherwise indicated, all of the following tables are: VDDA = VDD = 3.3V, RSET = 10k,
TA = +25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN MAX
(Note 9) TYP (Note 9)
UNIT
VDD, VDDA
Chip Supply Voltage
ADC disabled; see registers 0x0C, 0x41, and 3.0 3.3 3.6 V
“ADC DC Specifications” on page 7
VSL
IS-DIS
IS-ENA
Voltage Applied to Digital Bus
Supply Currents
Supply Currents
(1.8V or 3.3V); see Reg 0x08 Bits 6 and 7
Disable mode
Total supply current (VDDA, VDD) when chip is
enabled, DACs disabled:
Reg 0x06,0x07 = 0x01
1.6
0.78
3.6
10
0.90
V
µA
mA
IS-ENA
Supply Currents
Three outputs enabled mode 0;
All Reg. set to default value except:
Reg. 0x10 = 0x90;
Reg. 0x14,0x24,0x34 = 0x18;
Reg. 0x11,0x21,0x31 = 0x90;
Reg. 0x13,0x23,0x33 = 0xFF
37 48 mA
IS-ENA
Supply Currents No Bias
Three outputs enabled mode 0;
All Reg. set to default value except:
Reg. 0x10 = 0x90;
Reg. 0x14,0x24,0x34 = 0x00;
Reg. 0x11,0x21,0x31 = 0x90;
Reg. 0x13,0x23,0x33 = 0xFF
12 19 mA
IS-ENA
Supply Currents Low Bias
Three outputs enabled mode 0;
All Reg. set to default value except:
Reg. 0x10 = 0x90;
Reg. 0x14,0x24,0x34 = 0x01;
Reg. 0x11,0x21,0x31 = 0x90;
Reg. 0x13,0x23,0x33 = 0xFF
14 22 mA
IS-ENA
Supply Currents High Bias
Three outputs enabled mode 0;
All Reg. set to default value except:
Reg. 0x10 = 0x90;
Reg. 0x14,0x24,0x34 = 0x1F;
Reg. 0x11,0x21,0x31 = 0x90;
Reg. 0x13,0x23,0x33 = 0xFF
60 82 mA
6 FN7543.0
September 30, 2011

6 Page



ページ 合計 : 30 ページ
 
PDF
ダウンロード
[ ISL58315 データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
ISL58315

High Speed Triple Laser Diode Drivers

Intersil Corporation
Intersil Corporation


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap