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M4A3-256 の電気的特性と機能

M4A3-256のメーカーはLattice Semiconductorです、この部品の機能は「High Performance E2CMOS In-System Programmable Logic」です。


製品の詳細 ( Datasheet PDF )

部品番号 M4A3-256
部品説明 High Performance E2CMOS In-System Programmable Logic
メーカ Lattice Semiconductor
ロゴ Lattice Semiconductor ロゴ 




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M4A3-256 Datasheet, M4A3-256 PDF,ピン配置, 機能
ispMACH4A CPLD Family
High Performance E2CMOS®
In-System Programmable Logic
FEATURES
High-performance, E2CMOS 3.3-V & 5-V CPLD families
Flexible architecture for rapid logic designs
— Excellent First-Time-FitTM and ret feature
— SpeedLockingTM performance for guaranteed xed timing
— Central, input and output switch matrices for 100% routability and 100% pin-out retention
High speed
— 5.0ns tPD Commercial and 7.5ns tPD Industrial
— 182MHz fCNT
32 to 512 macrocells; 32 to 768 registers
44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
Flexible architecture for a wide range of design styles
— D/T registers and latches
— Synchronous or asynchronous mode
— Dedicated input registers
— Programmable polarity
— Reset/ preset swapping
Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— JTAG (IEEE 1149.1) compliant for boundary scan testing
— 3.3-V & 5-V JTAG in-system programming
— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system designs
— Programmable pull-up or Bus-FriendlyTM inputs and I/Os
— Hot-socketing
— Programmable security bit
— Individual output slew rate control
Advanced E2CMOS process provides high-performance, cost-effective solutions
Lead-free package options
Lead-
Free
Package
Options
Available!
Publication# ISPM4A Rev: M
Amendment/0
Issue Date: September 2006

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M4A3-256 pdf, ピン配列
GENERAL DESCRIPTION
The ispMACH4A family from Lattice offers an exceptionally flexible architecture and delivers a superior
Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools.
The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market,
greater flexibility and lower cost. The ispMACH 4A devices offer densities ranging from 32 to 512
macrocells with 100% utilization and 100% pin-out retention. The ispMACH 4A families offer 5-V (M4A5-
xxx) and 3.3-V (M4A3-xxx) operation.
ispMACH 4A products are 5-V or 3.3-V in-system programmable through the JTAG (IEEE Std. 1149.1)
interface. JTAG boundary scan testing also allows product testability on automated test equipment for
device connectivity.
All ispMACH 4A family members deliver First-Time-Fit and easy system integration with pin-out retention
after any design change and refit. For both 3.3-V and 5-V operation, ispMACH 4A products can deliver
guaranteed fixed timing as fast as 5.0 ns tPD and 182 MHz fCNT through the SpeedLocking feature when
using up to 20 product terms per output (Table 2).
Device
M4A3-32
M4A5-32
M4A3-64/32
M4A5-64/32
M4A3-64/64
M4A3-96
M4A5-96
M4A3-128
M4A5-128
M4A3-192
M4A5-192
M4A3-256/128
M4A5-256/128
M4A3-256/192
M4A3-256/160
M4A3-384
M4A3-512
-5
C
Table 2. ispMACH 4A Speed Grades
Speed Grade
-55 -6 -65 -7 -10 -12 -14
C, I C, I
I
C
C, I C, I
I
C
C, I C, I
I
C
C, I C, I
I
C
C, I C, I
I
C
C, I C, I
I
C C C, I C, I I
C C C, I I
C C, I I
C
C, I C, I
I
C C, I C, I I
Note:
1. C = Commercial, I = Industrial
ispMACH 4A Family
3


3Pages


M4A3-256 電子部品, 半導体
Table 4. Architectural Summary of ispMACH 4A devices
Macrocell-I/O Cell Ratio
Input Switch Matrix
Input Registers
Central Switch Matrix
Output Switch Matrix
ispMACH 4A Devices
M4A3-64/32, M4A5-64/32
M4A3-96/48, M4A5-96/48
M4A3-128/64, M4A5-128/64
M4A3-192/96, M4A5-192/96
M4A3-256/128, M4A5-256/128
M4A3-384
M4A3-512
M4A3-32/32
M4A5-32/32
M4A3-64/64
M4A3-256/160
M4A3-256/192
2:1 1:1
Yes Yes1
Yes No
Yes Yes
Yes Yes
The Macrocell-I/O cell ratio is defined as the number of macrocells versus the number of I/O cells
internally in a PAL block (Table 4).
The central switch matrix takes all dedicated inputs and signals from the input switch matrices and routes
them as needed to the PAL blocks. Feedback signals that return to the same PAL block still must go through
the central switch matrix. This mechanism ensures that PAL blocks in ispMACH 4A devices communicate
with each other with consistent, predictable delays.
The central switch matrix makes a ispMACH 4A device more advanced than simply several PAL devices on
a single chip. It allows the designer to think of the device not as a collection of blocks, but as a single
programmable device; the software partitions the design into PAL blocks through the central switch matrix
so that the designer does not have to be concerned with the internal architecture of the device.
Each PAL block consists of:
Product-term array
Logic allocator
Macrocells
Output switch matrix
I/O cells
Input switch matrix
Clock generator
Notes:
1. M4A3-64/64 internal switch matrix functionality embedded in central switch matrix.
6 ispMACH 4A Family

6 Page



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部品番号部品説明メーカ
M4A3-256

High Performance E2CMOS In-System Programmable Logic

Lattice Semiconductor
Lattice Semiconductor


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