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PDF AR7242 Data sheet ( Hoja de datos )
| Número de pieza | AR7242 | |
| Descripción | A High Performance And Cost-Effective Network Processor | |
| Fabricantes | Atheros | |
| Logotipo |  |
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Data Sheet
April 2011
AR7242: A High Performance And Cost-Effective Network
Processor
General Description
The Atheros AR7242 is a high performance
and cost effective network processor for access
point, router, and gateway applications. It
includes a MIPS 24Kc processor, PCI Express
1.1 host interface, integrated 10/100 Mbps
Fast Ethernet MAC/PHY, one RGMII port,
one USB 2.0 MAC/PHY, and external memory
interface for serial Flash, DDR1 or DDR2
interface, an I2S audio interface, a high-speed
UART, and GPIOs that can be used for LED
controls or other general purpose interface
configurations.
The AR7242 is a memory-centric architecture
including various DMA controlled interfaces
that access the DDR memory.
The AR7242 network processor, when paired
with the AR928x/AR938x/AR939x single
chip 802.11n MAC/BB/Radio family,
provides the best-in-class WLAN solution
capable of supporting 802.11b/g/n standards.
Features
■ Integrated MIPS 24 K 32-bit processor
operating at up to 400 MHz
■ 64 K instruction cache and 32 K data cache
■ Integrated 10/100 802.3 Ethernet LAN port
and one RGMII port
■ 16-bit DDR1 or DDR2 memory interface
supporting up to 400 M transfers per
second
■ An external serial Flash memory interface
(maximum 16 MBytes)
■ One USB 2.0 controller with built-in MAC/
PHY
■ High-speed UART and multiple GPIO pins
for general purpose I/O or LED control
■ A single lane PCI Express 1.1 interface that
can be used for interfacing to the AR928x/
AR938x/AR939x single chip 802.11n
MAC/BB/Radio
■ JTAG port support for processor core
■ 14 mm x 14 mm 128-pin LQFP lead-free
package
System Block Diagram
© 2010-2011 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Align®, Atheros XR®, Driving the Wireless Future®, Intellon®, ETHOS®, IQUE®, No
New Wires®, Orion® , PLC4Trucks®, Powerpacket®, Spread Spectrum Carrier®, SSC®, ROCm®, Super A/G®, Super G®, Super N®, The Air is Cleaner at 5-GHz®, Total 802.11®, U-
Nav®, Wake on Wireless®, Wireless Future. Unleashed Now.®, and XSPAN®, are registered by Atheros Communications, Inc. Atheros SST™, Signal-Sustain Technology™, ROCm™,
amp™, Install N Go™, Simpli-Fi™, SmartLink™, There is Here™, U-Map™, U-Tag™, and 5-UP™ are trademarks of Atheros Communications, Inc. The Atheros logo is a registered
trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice.
COMPANY CONFIDENTIAL
•1
1 page  
PRELIMINARY
(RST_GLOBAL_INTERRUPT_STA
TUS) .............................................. 60
4.5.8 Reset (RST_RESET) ..................... 61
4.5.9 Chip Revision ID
(RST_REVISION_ID) ................. 61
4.6 MBOX Registers ..................................... 62
4.6.1 Non-Destructive FIFO Status Query
(MBOX_FIFO_STATUS) ............ 63
4.6.2 Mailbox DMA Engine Policy
Control (MBOX_DMA_POLICY) 63
4.6.3 Mailbox 0 Rx DMA Descriptors
Base Address
(MBOX0_DMA_RX_DESCRIPTOR
_BASE) .......................................... 64
4.6.4 Mailbox 0 Rx DMA Control
(MBOX0_DMA_RX_CONTROL) 64
4.6.5 Mailbox 0 Tx DMA Descriptors Base
Address
(MBOX0_DMA_TX_DESCRIPTOR
_BASE) .......................................... 65
4.6.6 Mailbox 0 Tx DMA Control
(MBOX0_DMA_TX_CONTROL) 65
4.6.7 Mailbox FIFO Status
(MBOX_FRAME) ........................ 65
4.6.8 FIFO Timeout Period
(FIFO_TIMEOUT) ....................... 66
4.6.9 MBOX Related Interrupt Status
(MBOX_INT_STATUS) .............. 66
4.6.10 MBOX Related Interrupt Enables
(MBOX_INT_ENABLE) ............. 67
4.6.11 Reset and Clear MBOX FIFOs
(MBOX_FIFO_RESET) ............... 67
4.7 I2S Registers ............................................ 68
4.7.1 Configure Stereo Block
(STEREO0_CONFIG) ................. 68
4.7.2
4.7.3
4.7.4
4.7.5
4.7.6
Set Stereo Volume
(STEREO0_VOLUME) ............... 70
Tx Sample Counter
(STEREO0_TX_SAMPLE_CNT_LS
B) ................................................... 71
Tx Sample Counter
(STEREO0_TX_SAMPLE_CNT_MS
B) ................................................... 71
Rx Sample Counter
(STEREO0_RX_SAMPLE_CNT_LS
B) ................................................... 71
Rx Sample Counter
(STEREO0_RX_SAMPLE_CNT_MS
B) ................................................... 71
4.8 PCIE Configuration Space Registers ... 72
4.8.1 Vendor ID .................................... 72
4.8.2 Device ID ..................................... 72
4.8.3 Command .................................... 73
4.8.4 Status ............................................ 73
4.8.5 Revision ID .................................. 74
4.8.6 Class Code ................................... 74
4.8.7 Class Line Size ............................ 74
4.8.8 Master Latency Timer ................ 74
4.8.9 Header Type ................................ 74
4.8.10 Base Address 0 (BAR0) .............. 75
4.8.11 BAR0 Mask .................................. 75
4.8.12 Bus Number ................................ 76
4.8.13 Secondary Status ........................ 76
4.8.14 Memory Base ............................... 76
4.8.15 Memory Limit ............................. 76
4.8.16 Prefetchable Memory Base ........ 77
4.8.17 Prefetchable Memory Limit ...... 77
4.8.18 Capability Pointer ...................... 77
4.8.19 Interrupt Line .............................. 77
4.8.20 Interrupt Pin ................................ 78
4.8.21 Bridge Control ............................ 78
4.9 PCIE Control Registers ......................... 79
4.9.1 PCIE Application Control
(PCIE_APP) ................................. 80
4.9.2 PCIE Interrupt and Error
(PCIE_AER) ................................. 80
4.9.3 PCIE Power Management
(PCIE_PWR_MGMT) ................. 81
4.9.4 PCIE Electromechanical
(PCIE_ELEC) ............................... 81
4.9.5 PCIE Configuration (PCIE_CFG) 82
4.9.6 PCIE Receive Completion
(PCIE_RX_CNTL) ....................... 82
4.9.7 PCIE Reset (PCIE_RESET) ........ 83
4.9.8 PCIE PHY Configuration Data
(PCIE_PHY_CFG_DATA) ......... 83
4.9.9 PCIE MAC-PHY Interface Signals
(PCIE_MAC_PHY) ..................... 83
4.9.10 PCIE PHY-MAC Interface Signals
(PCIE_PHY_MAC) ..................... 84
4.9.11 PCIE Sideband Bus1
(PCIE_SIDEBAND1) .................. 84
4.9.12 PCIE Sideband Bus2
(PCIE_SIDEBAND2) .................. 84
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR7242 Network Processor • 5
April 2011 • 5
5 Page 
PRELIMINARY
Table 1-1 shows the multiplexed pins for the
AR7242,
Table 1-1. Multiplexed Pins[1][2]
LQFP-128
Pin GPIO Pin
EJTAG Pin
LED Pin
SPDIF/I2S Pin
SPI Pin UART Pin
GPIO_0
107
108 GPIO_1
GPIO_2
80
GPIO_3
76
GPIO_4
77
GPIO_5
78
81
GPIO_6
TDI (FN1, 0)
82 GPIO_7 TDO (FN1, 0)
84 GPIO_8 TMS (FN1, 0)
I2S_WS (FN2, 4)
I2S_CK (FN2, 3)
I2S_CK (FN1, 26)
I2S_WS (FN1, 26)
I2S_SD (FN1, 26)
SPI_CS_EN1
(FN1, 13)
SPI_CS_EN0
(FN1, 18)
SPI_CLK
(FN1, 18)
SPI_MOSI
(FN1, 18)
SPI_MISO
(FN1, 18)
GPIO_9
86
GPIO_10
87
GPIO_11
88
GPIO_12
89
GPO_13
90
91 GPO_14
LED_0
(FN1, 3)
I2S_MCK
(FN1, 26, 27)
I2S_MICIN (FN1,
26)
I2S_SD (FN2, 5)
SPDIF_OUT
(FN1, 30)
I2S_SD (FN2, 1)
UART_SIN
(FN1, 1)
UART_SOU
T (FN1, 1)
UART_RTS
(FN1, 2)
UART_CTS
(FN1, 2)
92 GPO_15
I2S_WS (FN2, 1)
109 GPO_16
I2S_CK (FN2, 1)
110 GPO_17
[1]Multiplexing of the GPIO pins is controlled by the “GPIO Function (GPIO_FUNCTION_1)” on page 48
and “Extended GPIO Function Control (GPIO_FUNCTION_2)” on page 49.
[2]Notations of (FNx, y) indicate that the pin is controlled by the particular register and bit. For example, (FN1, 30, 31)
indicates the GPIO_FUNCTION_1 register, bit [30] and bit [31], and (FN2, 1) indicates the GPIO_FUNCTION_2 register,
bit [1].
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR7242 Network Processor • 11
April 2011 • 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AR7242.PDF ] | |
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