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PDF 74C165 Data sheet ( Hoja de datos )
| Número de pieza | 74C165 | |
| Descripción | Parallel-Load 8-Bit Shift Register | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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December 1992
MM54C165 MM74C165
Parallel-Load 8-Bit Shift Register
General Description
The MM54C165 MM74C165 functions as an 8-bit parallel-
load serial shift register Data is loaded into the register
independent of the state of the clock(s) when PARALLEL
LOAD (PL) is low Shifting is inhibited as long as PL is low
Data is sequentially shifted from complementary outputs Q7
and Q7 highest-order bit (P7) first New serial data may be
entered via the SERIAL DATA (Ds) input Serial shifting oc-
curs on the rising edge of CLOCK1 or CLOCK2 Clock in-
puts may be used separately or together for combined
clocking from independent sources Either clock input may
be used also as an active-low clock enable To prevent dou-
ble-clocking when a clock input is used as an enable the
enable must be changed to a high level (disabled) only while
the clock is high
Features
Y Wide supply voltage range
Y Guaranteed noise margin
Y High noise immunity
Y Low power TTL compatibility
Y Parallel loading independent of clock
Y Dual clock inputs
Y Fully static operation
3V to 15V
1V
0 45 VCC (typ )
fan out of 2
driving 74L
Connection and Block Diagrams
Dual-In-Line Package
Top View
TL F 5897 – 2
Order Number MM54C165 or MM74C165
Please look into Section 8 Appendix D
for availability of various package types
TL F 5897 – 1
C1995 National Semiconductor Corporation TL F 5897
TL F 5897 – 3
RRD-B30M105 Printed in U S A
1 page  
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54C165J or MM74C165J
NS Package Number J16A
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet 74C165.PDF ] | |
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