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PDF ISL8272M Data sheet ( Hoja de datos )
| Número de pieza | ISL8272M | |
| Descripción | 50A Digital DC/DC PMBus Power Module | |
| Fabricantes | Intersil | |
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DATASHEET
50A Digital DC/DC PMBus Power Module
ISL8272M
The ISL8272M is a 50A step-down PMBus compliant digital
power module. Integrated in the module is a high performance
digital PWM controller, dual-phase power MOSFETs, inductors
and the passives. This high efficiency power module is capable
of delivering 50A without the need for airflow and heatsink.
The ISL8272M can be placed in a current sharing
configuration with up to 4 modules in parallel to deliver 200A
continuous current.
The ISL8272M operates with the ChargeMode™ control
architecture, which responds to a transient load within a single
switching cycle. The ISL8272M comes with operating in a pin
strap mode; output voltage, switching frequency device, SMBus
address, input UVLO, soft-start/stop and current sharing can be
programmed through external resistors. More configuration such
as fault limits, fault response, margining and sequencing can be
easily programmed via the PMBus interface. PMBus can be used
to monitor voltages, currents, temperatures and fault status. The
ISL8272M is supported by the PowerNavigator™ software, a
graphical user interface (GUI) that can be used to configure
modules to a desired solution.
The ISL8272M is built in a compact (18mmx23mmx7.5mm)
and low profile overmolded HDA package, suitable for
automated assembly by standard surface mount equipment.
Features
• Complete digital switch mode power supply
• Wide input voltage range: 4.5V to 14V
• Programmable output voltage range: 0.6V to 5V
• PMBus compliant communication interface
• Programmable VOUT, margining, UV/OV, UC/OC, UT/OT,
soft-start/stop, sequencing and external synchronization
• Monitor of VIN, VOUT, IOUT, temperature, duty cycle, switching
frequency, power-good and faults
• Fast response ChargeModeTM control architecture
• Multiphase current sharing with up to 4 modules
• ±1.0% VOUT accuracy over line, load and temperature
• Internal nonvolatile memory and fault logging
• Thermally enhanced HDA package
Applications
• Server, telecom, storage and datacom
• Industrial/ATE and networking equipment
• General purpose power for ASIC, FPGA, DSP and memory
Related Literature
• UG003, “ISL8272MEVAL1Z Evaluation Board User Guide”
• UG004, “ISL8272MEVAL2Z Evaluation Board User Guide”
VIN
CIN
ENABLE
VIN
VDD
EN
10µF 10µF
VR5
VR6
100k
2x10µF
6.65k
VDRV
VCC
VDRV1
VMON
ISL8272M
VOUT
VSENP
VSENN
VR
VR55
SGND
PGND
SCL
SDA
SALRT
VOUT
COUT
23mm
PMBUS
INTERFACE
7.5mm
18mm
NOTE:
1. Figure 1 represents a typical implementation of the ISL8272M. For PMBus
operation, it is recommended to tie the enable pin (EN) to SGND.
FIGURE 1. 50A APPLICATION CIRCUIT
FIGURE 2. A SMALL PACKAGE FOR HIGH POWER DENSITY
January 14, 2015
FN8670.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014, 2015. All Rights Reserved
Intersil (and design), ChargeMode, PowerNavigator and Digital-DC are trademarks owned by Intersil Corporation
or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.
1 page  
ISL8272M
Pin Descriptions (Continued)
PIN LABEL
C12 SDA
C13 SCL
D4 SS/
UVLO
D5 PG
D13 SYNC
E14 EN
E4 DDC
C5, D14, E15, TEST
F4, F15, G4
G14 ASCR
G15 V25
H3 VSENN
H4 VSENP
H16, J16, K16, SGND
M14
K14 VDD
L2 VR
L3, P11
SWD1,
SWD2
L14 VR5
M1 VCC
M5, M17, N5 PGND
M10 VR55
M13
VR6
N6, N16
VDRV
R8, R17
VDRV1
TYPE
DESCRIPTION
I/O Serial data. Connect to external host and/or to other Digital-DC™ devices. A pull-up resistor is required.
I/O Serial clock. Connect to external host and/or to other Digital-DC™ devices. A pull-up resistor is required.
I Soft-start/stop and undervoltage lockout selection pin. Used to set turn on/off delay and ramp time as well as input
UVLO threshold levels.
O Power-good output. Power-good output can be an open drain that requires a pull-up resistor or push-pull output that
can drive a logic input.
I/O Clock synchronization input. Used to set the frequency of the internal switch clock, to sync to an external clock or to
output internal clock.
I Enable pin. Logic high to enable the module output.
I/O A Digital-DC bus. This dedicated bus provides the communication between devices for features such as sequencing,
fault spreading and current sharing. The DDC pin on all Digital-DC devices should be connected together. A pull-up
resistor is required.
- Test pins. Don’t connect these pins.
I ChargeMode™ control ASCR parameters selection pin. Used to set ASCR gain and residual values.
PWR Internal 2.5V reference used to power internal circuitry. No external capacitor required for this pin.
I Differential output voltage sense feedback. Connect to negative output regulation point.
I Differential output voltage sense feedback. Connect to positive output regulation point.
PWR Signal grounds. Using multiple vias to connect the SGND pins to the internal SGND layer.
PWR Input supply voltage for controller. Connect VDD pad to VIN supply.
PWR Internal LDO bias pin. Tie VR to VR55 directly with a short loop trace.
PWR Switching node driving pins. Directly connect to the SW1 and SW2 pads with short loop wires.
PWR Internal 5V reference used to power internal circuitry. Place a 10µF decoupling capacitor for this pin.
PWR Internal LDO output. Connect VCC to VDRV for internal LDO driving.
PWR Power grounds. Using multiple vias to connect the PGND pins to the internal PGND layer.
PWR Internal 5.5V bias voltage for internal LDO use only. Tie VR55 pin directly to VR pin.
PWR Internal 6V reference used to power internal circuitry. Place a 10µF decoupling capacitor for this pin.
PWR Power supply for internal FET drivers. Connect 10μF bypass capacitor to each of these pins. These pins can be driven
by the internal LDO through VCC pin or by the external power supply directly. Keep the driving voltage between 4.5V
and 5.5V. For 5V input application, use external supply or connect this pin to VIN.
I Bias pin of the internal FET drivers. Always tie to VDRV.
Submit Document Feedback
5
FN8670.2
January 14, 2015
5 Page 
ISL8272M
Electrical Specifications VIN = VDD= 12V, fSW = 533kHz, TA = -40°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 14)
TYP
MAX
(Note 14)
UNITS
IOUT_RANGE
Output Current Range (Note 16)
IOUT_READ_ERR Output Current Read back Total Error
SOFT-START AND SEQUENCING
PMBus read at max load. VOUT = 1V
50 A
±3 A
tON_DELAY
tON_DELAY_ACCY
tON_RISE
Delay Time From Enable to VOUT Rise
tON_DELAY Accuracy
Output Voltage Ramp-Up Time
Configured using PMBus
Configured using PMBus. Single
module standalone
2
5000
ms
±2 ms
0.5 100 ms
tON_RISE_ACCY
Output Voltage Ramp-Up Time
Accuracy
Single module standalone
±250
µs
tOFF_DELAY
tOFF_DELAY_ACCY
tOFF_FALL
Delay Time From disable to VOUT Fall
tOFF_DELAY Accuracy
Output Voltage Fall Time
Configured using PMBus
Configured using PMBus. Single
module standalone
2
5000
ms
±2 ms
0.5 100 ms
tON_FALL_ACCY
POWER-GOOD
Output Voltage Fall Time Accuracy
Single module standalone
±250
µs
VPG_DELAY
Power-Good Delay
TEMPERATURE SENSE
Configured using PMBus
0
5000
ms
TSENSE_RANGE
INT_TEMPACCY
FAULT PROTECTION
Temperature Sense Range
Configurable via PMBus
Internal Temperature Sensor Accuracy Tested at +100°C
-50
-5
150 C
+5 C
VDD_UVLO_RANGE
VDD_UVLO_ACCY
VDD Undervoltage Threshold Range
VDD Undervoltage Threshold Accuracy
(Note 17)
Measured internally
4.18
±2
16 V
%FS
VDD_UVLO_DELAY
VOUT_OV_RANGE
VDD Undervoltage Response Time
VOUT Overvoltage Threshold Range
VOUT_UV_RANGE VOUT Undervoltage Threshold Range
VOUT_OV/UV_ACCY VOUT OV/UV Threshold Accuracy
(Note 15)
Factory default
Configured using PMBus
Factory default
Configured using PMBus
10
1.05VOUT
0
-2
1.15VOUT
0.85VOUT
VOUT_MAX
0.95VOUT
+2
µs
V
V
V
V
%
VOUT_OV/UV_DELAY
ILIMIT_ACCY
VOUT OV/UV Response Time
Output Current Limit Set-Point
Accuracy (Note 17)
Tested at IOUT_OC_FAULT_LIMIT = 50A
10
±10
µs
% FS
ILIMIT_DELAY
Output Current Fault Response Time Factory default
(Note 18)
3 tSW
TJUNCTION
Over-temperature Protection
Threshold
(Controller Junction Temperature)
Factory default
Configured using PMBus
125 C
-40 125 C
TJUNCTION_HYS Thermal Protection Hysteresis
15 C
Submit Document Feedback 11
FN8670.2
January 14, 2015
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ISL8272M.PDF ] | |
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