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G65SC816 の電気的特性と機能

G65SC816のメーカーはCalifornia Micro Devices Corpです、この部品の機能は「CMOS 8/16-BIT MICROPROCESSOR」です。


製品の詳細 ( Datasheet PDF )

部品番号 G65SC816
部品説明 CMOS 8/16-BIT MICROPROCESSOR
メーカ California Micro Devices Corp
ロゴ California Micro Devices Corp ロゴ 




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G65SC816 Datasheet, G65SC816 PDF,ピン配置, 機能
Microcircuits
G65SC802
G65SC816
CMOS 8-Bit/16-Bit Microprocessor Family
Features
• Advanced CMOS design for low power consumption and increased
noise immunity
• Emulation mode for total software compatibility with 6502 designs
• Full 16-bit ALU, Accumulator, Stack Pointer, and Index Registers
• Direct Register for “zero page” addressing
• 24 addressing modes (including 13 original 6502 modes)
• Wait for Interrupt (WAI) and Stop the Clock (STP) instructions for
reduced power consumption and decreased interrupt latency
• 91 instructions with 255 opcodes
• Co-Processor (COP) instruction and associated vector
• Powerful Block Move instructions
Features (G65SC802 Only)
• 8-Bit Mode with both software and hardware (pin-to-pin) com­
patibility with 6502 designs (64 KByte memory space)
• Program selectable 16-bit operation
• Choice of external or on-board clock generation
Features (G65SC816 Only)
• Full 16-bit operation with 24 address lines for 16 MByte memory
• Program selectable 8-Bit Mode for 6502 coding compatibility.
• Valid Program Address (VPA) and Valid Data Address (VDA) outputs
for dual cache and DMA cycle steal implementation
• Vector Pull (VP) output indicates when interrupt vectors are being
fetched. May be used for vectoring/prioritizing interrupts
• Abort interrupt and associated vector for interrupting any instruction
without modifying internal registers
• Memory Lock (ML) for multiprocessor system implementation
General Description
The G65SC802 and G65SC816 are ADV-CMOS (ADVanced CMOS) 16-
bit microprocessors featuring total software compatibility with 8-bit
NMOS and CMOS 6500 series microprocessors. The G65SC802 is pin-
to-pin compatible with 8-bit 6502 devices currently available, while also
providing full 16-bit internal operation. The G65SC816 provides 24 ad­
dress lines for 16 MByte addressing, while providing both 8-bit and 16-bit
operation.
Each microprocessor contains an Emulation (E) mode for emulating
8-bit NMOS and CMOS 6500-Series microprocessors. A software switch
determines whether the processor is in the 8-bit emulation mode or in
the Native 16-bit mode. This allows existing 8-bit system designs to use
the many powerful features of the G65SC802 and G65SC816.
The G65SC802 and G65SC816 provide the system engineer with many
powerful features and options. A 16-bit Direct Page Register is provided
to augment the Direct Page addressing mode, and there are separate
Program Bank Registers for 24-bit memory addressing. Other valuable
features include:
• An Abort input which can interrupt the current instruction without
modifying internal registers.
• Valid Data Address (VDA) and Valid Program Address (VPA) outputs
which facilitate dual cache memory by indicating whether a data or
program segment is being accessed.
• Vector modification by simply monitoring the Vector Pull (VP) output.
• Block Move instructions.
GTE Microcircuits’ G65SC802and G65SC816 microprocessors offer the
design engineer a new freedom of design and application, and the many
advantages of state-of-the-art ADV-CMOS technology.
Simplified Block Diagram
l<2 1
DO-D7 (802)
D0/A16-D7/A23 (816)
ADVANCE INFORMATION
This isadvanced information and specifications
are subject to change without notice.

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G65SC816 pdf, ピン配列
AC Characteristics (G65SC816): vdd =s.ov ±5%, Vss =ov, Ta =o°c to +70°c
Parameter
Cycle Time
Clock Pulse Width Low
Clock Pulse Width High
Fall Time, Rise Time
A0-A15 Hold Time
A0-A15 Setup Time
A16-A23 Hold Time
A16-A23 Setup Time
Access Time
Read Data Hold Time
Read Data Setup Time
Write Data Delay Time
Write Data Hold Time
Processor Control Setup Time
M/X Output Setup Time
M/X Output Hold Time
E Output Setup Time
Capacitive Load (Address, Data, and R/W)
BE to High Impedance State
BE to Valid Data
Symbol
tCYC
tPWL
tPWH
tF, tR
tAH
tADS
tBH
tBAS
tACC
tDHR
tDSR
tMOS
tDHW
tPCS
tXMS
tXMH
tES
C ext
tBHZ
tBVD
2 MHz
Min Max
500 DC
240
240
10
10
100
10
100
365
10
40
100
10
125
50
10
50
100
30
30
4 MHz
Min Max
250 DC
120
120
10
10
75
10
90
130
10
30
70
10
100
50
10
50
100
30
30
6 MHz
Min Max
167 DC
80
80
5
10
60
10
65
87
10
20
60
10
75
25
5
25
35
30
30
8 MHz
Min Max
125 DC
60
60
5
10
40
10
45
70
)o
15
40
10
50
15
5
15
35
30
30
Unit
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
PF
nS
nS
Timing Diagram (G65SC802)
3


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G65SC816 電子部品, 半導体
Signal Description
The following Signal Description applies to both the G65SC802 and the
G65SC816 except as otherwise noted.
Abort (ABORT)—G65SC816
The Abort input is used to abort instructions (usually due to an Address
Bus condition). A negative transition will inhibit modification of any in­
ternal register during the current instruction. Upon completion of this
instruction, an interrupt sequence is initiated. The location of the aborted
opcode is stored as the return address in stack memory. The Abort vector
address is 00FFF8.9 (Emulation mode) or 00FFE8.9 (Native mode).
Since ABORT is an edge-sensitive input, an Abort will occur whenever
there is a negative transition on the ABORT line.
Address Bus (A0-A15)
These sixteen output lines form the Address Bus for memory and I/O
exchange on the Data Bus. When using the G65SC816, the address lines
may be set to the high impedance state by the Bus Enable (BE) signal.
Bus Enable (BE)
The Bus Enable input signal aljows external control of the Address and
Data Buffers, as well as the R/W signal. With Bus Enable high, the R/W
and Address Buffers are active. The Data/Address Buffers are active
during the first half of every cycle and the second half of a write cycle.
When BE is low, these buffers are disabled. Bus Enable is an asynchro­
nous signal.
Data Bus (D0-D7)—G65SC802
The eight Data Bus lines provide an 8-bit bidirectional Data Bus for use
during data exchanges between the microprocessor and external mem­
ory or peripherals. Two memory cycles are required for the transfer of
16-bit values.
Data/Address Bus (D0/A16-D7/A23)—G65SC816
These eight lines multiplex address bits A16-A23 with the data value. The
address is present during the first half of a memory cycle, and the data
value is read or written during the second half of the memory cycle. Two
memory cycles are required to transfer 16-bit values. These lines may be
set to the high impedance state by the Bus Enable (BE) signal.
Emulation Status (E)—G65SC816
The Emulation Status output reflects the state of the Emulation (E) mode
flag in the Processor Status (P) Register. This signal may be thought of
as an opcode extension and used for memory and system management.
Interrupt Request (IRQ)
The Interrupt Request input signal is used to request that an interrupt
sequence be initiated. When the IRQ Disable (I) flag is cleared, a low in­
put logic level initiates an interrupt sequence after the current instruc­
tion is completed. The Wait for Interrupt (WAI) instruction may be ex­
ecuted to ensure the interrupt will be recognized immediately. The Inter­
rupt Request vector address is OOFFFE.F (Emulation mode) or OOFFEE.F
(Native mode). Since IRQ is a level-sensitive input, an interrupt will
occur if the interrupt source was not cleared since the last interrupt.
Also, no interrupt will occur if the interrupt source is cleared prior to
interrupt recognition.
Memory Lock (ML)—G65SC816
The Memory Lock output may be used to ensure the integrity of Read-
Modify-Write instructions in a multiprocessor system. Memory Lock
indicates the need to defer arbitration of the next bus cycle. Memory
Lock is low during the last three or five cycles of ASL, DEC, INC, LSR,
ROL, ROR, TRB, and TSB memory referencing instructions, depending
on the state of the M flag.
Memory/Index Select Status (M/X)—G65SC816
This multiplexed output reflects the state of the Accumulator (M) and
Index (X) select flags (bits 5 and 4 of the Processor Status (P) Register.
Flag M is valid during the Phase 2 clock negative transition and Flag X is
valid during the Phase 2 clock positive transition. These bits may be
thought of as opcode extensions and may be used for memory and
system management.
Non-Maskable Interrupt (NMI)
A negative transition on the NMI input initiates an interrupt sequence. A
high-to-low transition initiates an interrupt sequence after the current
instruction is completed. The Wait for Interrupt (WAI) instruction may be
executed to ensure that the interrupt will be recognized immediately. The
Non-Maskable Interrupt vector address is OOFFFA.B (Emulation mode)
or OOFFEA.B (Native mode). Since NMI is an edge-sensitive input, an
interrupt will occur if there is a negative transition while servicing a pre­
vious interrupt. Also, no interrupt will occur if NMI remains low.
Phase 1 Out (01 (OUT))—G65SC802
This inverted clock output signal provides timing for external read and
write operations. Executing the Stop (STP) instruction holds this clock
in the low state.
Phase 2 In (02 (IN))
This is the system clock input to the microprocessor internal clock gen­
erator (equivalent to 00 (IN) on the 6502). During the low power Standby
Mode, 02 (IN) should be held in the high state to preserve the contents
of internal registers.
Phase 2 Out (02 (OUT))—G65SC802
This clock output signal provides timing for external read and write op­
erations. Addresses are valid (after the Address Setup Time (Tads)) fol­
lowing the negative transition of Phase 2 Out. Executing the Stop (STP)
instruction holds Phase 2 Out in the High state.
Read/Write^R/W)
When the R/W output signal is in the high state, the microprocessor is
reading data from memory or I/O. When in the low state, the Data Bus
contains valid data from the microprocessor which is to be stored at the
addressed memory location. When using the G65SC816, the R/W signal
may be set to the high impedance state by Bus Enable (BE).
Ready (RDY)
This bidirectional signal indicates that a Wait for Interrupt (WAI) instruc­
tion has been executed allowing the user to halt operation of the micro­
processor. A low input logic level will halt the microprocessor in its cur­
rent state (note that when in the Emulation mode, the G65SC802 stops
only during a read cycle). Returning RDY to the active high state allows
the microprocessor to continue following the next Phase 2 In Clock
negative transition. The RDY signal is internally pulled low following the
execution of a Wait for Interrupt (WAI) instruction, and then returned to
the high state when a RES, ABORT, NMI, or IRQ external interrupt is
provided. This feature may be used to eliminate interrupt latency by
placing the WAI instruction at the beginning of the IRQ servicing routine.
If the IRQ Disable flag has been set, the next instruction will be executed
when the IRQ occurs. The processor will not stop after a WAI instruction
if RDY has been forced to a high state. The Stop (STP) instruction has
no effect on RDY.
Reset (RES)
The Reset input is used to initialize the microprocessor and start pro­
gram execution. The Reset input buffer has hysteresis such that a simple
R-C timing circuit may be used with the internal pullup device. The RES
signal must be held low for at least two clock cycles after Vdd reaches
operating voltage. Ready (RDY) has no effect while RES is being held low.
During this Reset conditioning period, the following processor initializa­
tion takes place:
D 0000
DB = 00
PB = 00
Registers
SH = 01
XH = 00
YH = 00
N V M X D I Z C/E
P * * 1 1 0 1 * */1 * = Not Initialized
STP and WAI instructions are cleared.
E =1
M/X = 1
R/W = 1
SYNC = 0
Signals
VDA = 0
VP = 1
VPA = 0
nen_Reset is brought high, an interrupt sequence is initiated:
* R/W remains in the high state during the stack address cycles.
• The Reset vector address is 00FFFC.D.
Set Overflow (SO)—G65SC802
A negative transition on this input sets the Overflow (V) flag, bit 6 of the
Processor Status (P) Register.
Synchronize (SYNC)—G65SC802
The SYNC output is provided to identify those cycles during which the
microprocessor is fetching an opcode. The SYNC signal is high during
an opcode fetch cycle, and when combined with Ready (RDY), can be
used for single instruction execution.
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部品番号部品説明メーカ
G65SC816

CMOS 8/16-BIT MICROPROCESSOR

California Micro Devices Corp
California Micro Devices Corp


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