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G28F640J5-150 の電気的特性と機能

G28F640J5-150のメーカーはIntel Corporationです、この部品の機能は「StrataFlash MEMORY TECHNOLOGY 32 AND 64 MBIT」です。


製品の詳細 ( Datasheet PDF )

部品番号 G28F640J5-150
部品説明 StrataFlash MEMORY TECHNOLOGY 32 AND 64 MBIT
メーカ Intel Corporation
ロゴ Intel Corporation ロゴ 




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G28F640J5-150 Datasheet, G28F640J5-150 PDF,ピン配置, 機能
E
ADVANCE INFORMATION
INTEL StrataFlash™ MEMORY TECHNOLOGY
32 AND 64 MBIT
28F320J5 and 28F640J5
n High-Density Symmetrically-Blocked
Architecture
64 128-Kbyte Erase Blocks (64 M)
32 128-Kbyte Erase Blocks (32 M)
n 5 V VCC Operation
2.7 V I/O Capable
n Configurable x8 or x16 I/O
n 120 ns Read Access Time (32 M)
150 ns Read Access Time (64 M)
n Enhanced Data Protection Features
Absolute Protection with
VPEN = GND
Flexible Block Locking
Block Erase/Program Lockout
during Power Transitions
n Industry-Standard Packaging
µBGA* Package, SSOP and TSOP
Packages (32 M)
n Cross-Compatible Command Support
Intel Basic Command Set
Common Flash Interface
Scaleable Command Set
n 32-Byte Write Buffer
6 µs per Byte Effective
Programming Time
n 640,000 Total Erase Cycles (64 M)
320,000 Total Erase Cycles (32 M)
10,000 Erase Cycles per Block
n Automation Suspend Options
Block Erase Suspend to Read
Block Erase Suspend to Program
n System Performance Enhancements
STS Status Output
n Intel StrataFlash™ Memory Flash
Technology
Capitalizing on two-bit-per-cell technology, Intel StrataFlash™ memory products provide 2X the bits in 1X the
space. Offered in 64-Mbit (8-Mbyte) and 32-Mbit (4-Mbyte) densities, Intel StrataFlash memory devices are
the first to bring reliable, two-bit-per-cell storage technology to the flash market.
Intel StrataFlash memory benefits include: more density in less space, lowest cost-per-bit NOR devices,
support for code and data storage, and easy migration to future devices.
Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, Intel StrataFlash
memory devices take advantage of 400 million units of manufacturing experience since 1988. As a result,
Intel StrataFlash components are ideal for code or data applications where high density and low cost are
required. Examples include networking, telecommunications, audio recording, and digital imaging.
By applying FlashFile™ memory family pinouts, Intel StrataFlash memory components allow easy design
migrations from existing 28F016SA/SV, 28F032SA, and Word-Wide FlashFile memory devices (28F160S5
and 28F320S5).
Intel StrataFlash memory components deliver a new generation of forward-compatible software support. By
using the Common Flash Interface (CFI) and the Scaleable Command Set (SCS), customers can take
advantage of density upgrades and optimized write capabilities of future Intel StrataFlash memory devices.
Manufactured on Intel’s 0.4 micron ETOX™ V process technology, Intel StrataFlash memory provides the
highest levels of quality and reliability.
January 1998
Order Number: 290606-004

1 Page





G28F640J5-150 pdf, ピン配列
E
INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
CONTENTS
PAGE
1.0 PRODUCT OVERVIEW ...................................5
2.0 PRINCIPLES OF OPERATION .....................11
2.1 Data Protection ..........................................12
3.0 BUS OPERATION .........................................12
3.1 Read ..........................................................13
3.2 Output Disable ...........................................13
3.3 Standby......................................................13
3.4 Reset/Power-Down ....................................13
3.5 Read Query................................................14
3.6 Read Identifier Codes.................................14
3.7 Write ..........................................................14
4.0 COMMAND DEFINITIONS ............................14
4.1 Read Array Command................................18
4.2 Read Query Mode Command.....................18
4.2.1 Query Structure Output .......................18
4.2.2 Query Structure Overview ...................20
4.2.3 Block Status Register ..........................21
4.2.4 CFI Query Identification String.............22
4.2.5 System Interface Information...............23
4.2.6 Device Geometry Definition .................24
4.2.7 Primary-Vendor Specific Extended
Query Table .......................................25
4.3 Read Identifier Codes Command ...............26
4.4 Read Status Register Command................27
4.5 Clear Status Register Command................27
4.6 Block Erase Command ..............................27
4.7 Block Erase Suspend Command................27
4.8 Write to Buffer Command...........................28
4.9 Byte/Word Program Commands.................28
4.10 Configuration Command...........................29
4.11 Set Block and Master Lock-Bit
Commands................................................ 29
4.12 Clear Block Lock-Bits Command..............30
PAGE
5.0 DESIGN CONSIDERATIONS ........................40
5.1 Three-Line Output Control..........................40
5.2 STS and Block Erase, Program, and Lock-
Bit Configuration Polling ............................40
5.3 Power Supply Decoupling ..........................40
5.4 VCC, VPEN, RP# Transitions........................40
5.5 Power-Up/Down Protection ........................41
5.6 Power Dissipation.......................................41
6.0 ELECTRICAL SPECIFICATIONS..................42
6.1 Absolute Maximum Ratings........................42
6.2 Operating Conditions..................................42
6.3 Capacitance ...............................................42
6.4 DC Characteristics .....................................43
6.5 AC Characteristics— Read-Only
Operations.................................................45
6.6 AC Characteristics— Write Operations.......48
6.7 Block Erase, Program, and Lock-Bit
Configuration Performance........................51
7.0 ORDERING INFORMATION.........................52
8.0 ADDITIONAL INFORMATION ......................53
ADVANCE INFORMATION
3


3Pages


G28F640J5-150 電子部品, 半導体
INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
E
are valid. Likewise, the device has a wake time
(tPHWL) from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset
and the status register is cleared.
The Intel StrataFlash memory devices are
available in several package types. The 64-Mbit is
available in 56-lead SSOP (Shrink Small Outline
Package) and µBGA* package (micro Ball Grid
Array). The 32-Mbit is available in 56-lead TSOP
(Thin Small Outline Package), 56-lead SSOP, and
56-bump µBGA packages. Figures 2, 3, and 4
show the pinouts.
VCCQ
32-Mbit: A0- A21
64-Mbit: A0 - A22
Input Buffer
Address
Latch
Address
Counter
DQ0 - DQ15
Y-Decoder
X-Decoder
Output Buffer
Input Buffer
Query
Identifier
Register
Status
Register
Data
Comparator
Y-Gating
Multiplexer
32-Mbit: Thirty-two
64-Mbit: Sixty-four
128-Kbyte Blocks
Command
User
Interface
I/O Logic
CE
Logic
VCC
BYTE#
CE0
CE1
CE2
WE#
OE#
RP#
Write State
Machine
Program/Erase
Voltage Switch
STS
VPEN
VCC
GND
0606_01
Figure 1. Intel StrataFlash™ Memory Block Diagram
6 ADVANCE INFORMATION

6 Page



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部品番号部品説明メーカ
G28F640J5-150

StrataFlash MEMORY TECHNOLOGY 32 AND 64 MBIT

Intel Corporation
Intel Corporation


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