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PDF IS61LV12816LL Data sheet ( Hoja de datos )
| Número de pieza | IS61LV12816LL | |
| Descripción | 128K x 16 HIGH-SPEED CMOS STATIC RAM | |
| Fabricantes | Integrated Silicon Solution | |
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IS61LV12816L
IS61LV12816LL
ISSI®
128K x 16 HIGH-SPEED CMOS STATIC RAM PRELIMINARYINFORMATION
WITH 3.3V SUPPLY
JULY 2002
FEATURES
• High-speed access time:
IS61LV12816L: 8, 10 ns
IS61LV12816LL: 12, 15 ns
• Operating Current:
IS61LV12816L: 50mA (typ.)
IS61LV12816LL: 25mA (typ.)
• Stand by Current:
IS61LV12816L: 500µA (typ.)
IS61LV12816LL: 250µA(typ.)
• TTL and CMOS compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The ISSI IS61LV12816L/IS61LV12816LL is a high-speed,
2,097,152-bit static RAM organized as 131,072 words by
16 bits. It is fabricated using ISSI's high-performance
CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields access
times as fast as 8 ns with low power consumption.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS61LV12816L/IS61LV12816LL is packaged in the
JEDEC standard 44-pin TSOP, 44-pin LQFP, and 48-pin
mini BGA (6mm x 8mm).
A0-A16
DECODER
128Kx16
MEMORY ARRAY
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CS2
CS1
OE
WE
UB
LB
CONTROL
CIRCUIT
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARYINFORMATION Rev. 00B
07/30/02
1
1 page  
IS61LV12816L, IS61LV12816LL
ISSI ®
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
IS61LV12816L
Symbol
ICC
ISB1
ISB2
Parameter
Vcc Operating
Supply Current
TTL Standby
Current
(TTL Inputs)
CMOS Standby
Current
(CMOS Inputs)
Test Conditions
VCC = Max., CE = VIL
IOUT = 0 mA, f = Max.
VCC = Max.,
VIN = VIH or VIL
CE • VIH, f = max
VCC = Max.,
CE - VCC – 0.2V,
VIN > VCC – 0.2V, or
VIN - 0.2V, f = 0
Com.
Ind.
Com.
Ind.
Com.
Ind.
-8 ns
Min. Max.
— 65
— 70
— 30
— 35
-10 ns
Min. Max.
— 60
— 65
— 25
— 30
—3
—4
—3
—4
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Unit
mA
mA
mA
mA
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
IS61LV12816LL
Symbol
ICC
ISB1
ISB2
Parameter
Vcc Operating
Supply Current
TTL Standby
Current
(TTL Inputs)
CMOS Standby
Current
(CMOS Inputs)
Test Conditions
VCC = Max., CE = VIL
IOUT = 0 mA, f = Max.
VCC = Max.,
VIN = VIH or VIL
CE • VIH, f = max
VCC = Max.,
CE - VCC – 0.2V,
VIN > VCC – 0.2V, or
VIN - 0.2V, f = 0
Com.
Ind.
Com.
Ind.
Com.
Ind.
-12 ns
Min. Max.
— 50
— 60
— 15
— 20
-15 ns
Min. Max.
— 45
— 50
— 15
— 20
— 200
— 300
— 200
— 300
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Unit
mA
mA
µA
µA
CAPACITANCE(1)
Symbol Parameter
Conditions
Max.
Unit
CIN Input Capacitance
VIN = 0V
6 pF
COUT
Input/Output Capacitance
VOUT = 0V
8 pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
07/30/02
5
5 Page 
IS61LV12816L, IS61LV12816LL
ISSI ®
WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3)
ADDRESS
t WC
ADDRESS 1
t WC
ADDRESS 2
OE
CE LOW
t SA
WE
UB, LB
DOUT
DIN
t PBW
t HZWE
DATA UNDEFINED
WORD 1
HIGH-Z
t SD
DATAIN
VALID
t HA
t SA
t PBW
WORD 2
t HA
t LZWE
t HD
t SD
DATAIN
VALID
t HD
UB_CEWR4.eps
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is refer
enced to the rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
07/30/02
11
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| PDF Descargar | [ Datasheet IS61LV12816LL.PDF ] | |
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