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SEN06464H2CG1SA-25ER の電気的特性と機能

SEN06464H2CG1SA-25ERのメーカーはSwissbitです、この部品の機能は「512MB DDR2 - SDRAM SO-DIMM」です。


製品の詳細 ( Datasheet PDF )

部品番号 SEN06464H2CG1SA-25ER
部品説明 512MB DDR2 - SDRAM SO-DIMM
メーカ Swissbit
ロゴ Swissbit ロゴ 




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SEN06464H2CG1SA-25ER Datasheet, SEN06464H2CG1SA-25ER PDF,ピン配置, 機能
Data Sheet
Rev.1.0 18.02.2014
512MB DDR2 SDRAM SO-DIMM
200 Pin SO-DIMM
SEN06464H2CG1SA-xx[E/W]R
Up to PC2-6400 in FBGA Technology
RoHS compliant
Options:
Data Rate / Latency
Marking
DDR2 667 MT/s CL5
DDR2 800 MT/s CL6
-30
-25
Module Density
512MB with 4 dies and 1 rank
Standard Grade
Grade E
Grade W
(tA) 0°C to 70°C
(tC) 0°C to 85°C
(tA) 0°C to 85°C
(tC) 0°C to 95°C *)
(tA) -40°C to 85°C
(tC) -40°C to 95°C *)
*) The refresh rate has to be doubled when 85°C<TC<95°C
Features:
200-pin 64-bit DDR2 Small Outline, Dual-In-Line Double
Data Rate Synchronous DRAM Module
Module organization: single rank 64M x 64
VDD = 1.8V ±0.1V, VDDQ 1.8V ±0.1V
1.8V I/O ( SSTL_18 compatible)
Serial Presence Detect (SPD) EEPROM
Gold-contact pad
This module is fully pin and functional compatible to the
JEDEC PC2-6400 spec. and JEDEC- Standard MO-224.
(see www.jedec.org)
The pcb and all components are manufactured according
to the RoHS compliance specification
[EU Directive 2002/95/EC Restriction of Hazardous
Substances (RoHS)]
DDR2 - SDRAM component Samsung
K4T1G164QG
64Mx16 DDR2 SDRAM in FBGA-84 package
Four bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Eight internal device banks for concurrent operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency 1 tCK
Programmable burst length: 4 or 8
Adjustable data-output drive strength
On-die termination (ODT)
Environmental Requirements:
Operating temperature (ambient)
standard Grade
0°C to 70°C
E-Grade
0°C to 85°C
W-Grade
Operating Humidity
-40°C to 85°C
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C
Figure: mechanical dimensions1
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
1if no tolerances specified ± 0.15mm
www.swissbit.com
Page 1
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1 Page





SEN06464H2CG1SA-25ER pdf, ピン配列
CK0#
VDD
VREF
VSS
VDDSPD
SCL
SDA
SA0 SA1
ODT0
NC
Data Sheet
Clock Inputs, negative line
Supply Voltage (1.8V+0.1V)
Input / Output Reference
Ground
Serial EEPROM Positive Power Supply
Serial Clock for Presence Detect
Serial Data Out for Presence Detect
Presence Detect Address Inputs
On-Die Termination
No Connection
Rev.1.0 18.02.2014
Pin Configuration
PIN #
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
Front Side
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
PIN #
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
Back Side
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
NC
DM2
PIN #
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
Front Side
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC(S1#)
VDD
NC(ODT1)
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
PIN #
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
Back Side
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC(A13)
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
Page 3
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3Pages


SEN06464H2CG1SA-25ER 電子部品, 半導体
Data Sheet
Rev.1.0 18.02.2014
MAXIMUM ELECTRICAL DC CHARACTERISTICS
PARAMETER/ CONDITION
VDD Supply Voltage relative to VSS
I/O VDD Supply Voltage relative to VSS
Voltage on any pin relative to VSS
INPUT LEAKAGE CURRENT
Any input 0V ≤ VIN VDD, VREF pin 0V ≤ VIN ≤ 0.95V
(All other pins not under test = 0V)
SYMBOL
VDD
VDDQ
VIN, VOUT
II
Command/Address
RAS#, CAS#, WE#, S#, CKE
CK, CK#
DM
OUTPUT LEAKAGE CURRENT
(DQ’s and ODT are disabled; 0V ≤ VOUT VDDQ)
IOZ
DQ, DQS, DQS#
VREF LEAKAGE CURRENT ; VREF is on a valid level
IVREF
MIN
-0.5
-0.5
-0.5
-40
-20
-5
-5
-16
MAX
2.3
2.3
2.3
40
20
5
5
UNITS
V
V
V
µA
µA
16 µA
DC OPERATING CONDITIONS
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
VDDL Supply Voltage
I/O Reference Voltage
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
SYMBOL
VDD
VDDQ
VDDL
VREF
VTT
VIH (DC)
VIL (DC)
MIN
1.7
1.7
1.7
0.49 x VDDQ
VREF 0.04
VREF + 0.125
-0.3
NOM
1.8
1.8
1.8
0.50 x VDDQ
VREF
MAX
1.9
1.9
1.9
0.51x VDDQ
VREF + 0.04
VDDQ + 0.3
VREF 0.125
UNITS
V
V
V
V
V
V
V
AC INPUT OPERATING CONDITIONS
PARAMETER/ CONDITION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
SYMBOL
VIH (AC)
VIL (AC)
MIN
VREF + 0.25
-
MAX
-
VREF - 0.25
UNITS
V
V
CAPACITANCE
At DDR2 data rates, it is recommended to simulate the performance of the module to achieve optimum values.
When inductance and delay parameters associated with trace lengths are used in simulations, they are
significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then
render a considerably more accurate result. JEDEC modules are now designed by using simulations to close
timing budgets.
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
Page 6
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6 Page



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部品番号部品説明メーカ
SEN06464H2CG1SA-25ER

512MB DDR2 - SDRAM SO-DIMM

Swissbit
Swissbit


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