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RTL8201N-GR の電気的特性と機能

RTL8201N-GRのメーカーはREALTEKです、この部品の機能は「SINGLE-CHIP/PORT 10/100M FAST ETHERNET PHYCEIVER」です。


製品の詳細 ( Datasheet PDF )

部品番号 RTL8201N-GR
部品説明 SINGLE-CHIP/PORT 10/100M FAST ETHERNET PHYCEIVER
メーカ REALTEK
ロゴ REALTEK ロゴ 




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RTL8201N-GR Datasheet, RTL8201N-GR PDF,ピン配置, 機能
RTL8201N-GR
SINGLE-CHIP/PORT
10/100M FAST ETHERNET PHYCEIVER
WITH AUTO MDIX
DATASHEET
Rev. 1.1
22 August 2006
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw

1 Page





RTL8201N-GR pdf, ピン配列
RTL8201N
Datasheet
Table of Contents
1. GENERAL DESCRIPTION................................................................................................................................................1
2. FEATURES...........................................................................................................................................................................2
3. APPLICATIONS ..................................................................................................................................................................2
4. BLOCK DIAGRAM.............................................................................................................................................................3
5. PIN ASSIGNMENTS ...........................................................................................................................................................4
5.1. GREEN PACKAGE AND VERSION IDENTIFICATION .........................................................................................................4
6. PIN DESCRIPTIONS ..........................................................................................................................................................5
6.1. MII INTERFACE ............................................................................................................................................................5
6.2. SNI (SERIAL NETWORK INTERFACE) 10MBPS ONLY ....................................................................................................6
6.3. CLOCK INTERFACE .......................................................................................................................................................6
6.4. 10MBPS/100MBPS NETWORK INTERFACE....................................................................................................................7
6.5. DEVICE CONFIGURATION INTERFACE ...........................................................................................................................7
6.6. LED INTERFACE...........................................................................................................................................................8
6.7. POWER PINS .................................................................................................................................................................8
6.8. RESET AND OTHER PINS...............................................................................................................................................8
7. REGISTER DESCRIPTIONS ............................................................................................................................................9
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
7.10.
7.11.
7.12.
REGISTER 0 BASIC MODE CONTROL REGISTER ............................................................................................................9
REGISTER 1 BASIC MODE STATUS REGISTER .............................................................................................................10
REGISTER 2 PHY IDENTIFIER REGISTER 1..................................................................................................................11
REGISTER 3 PHY IDENTIFIER REGISTER 2..................................................................................................................11
REGISTER 4 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (ANAR) ....................................................................11
REGISTER 5 AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (ANLPAR)......................................................12
REGISTER 6 AUTO-NEGOTIATION EXPANSION REGISTER (ANER) .............................................................................13
REGISTER 16 NWAY SETUP REGISTER (NSR).............................................................................................................13
REGISTER 17 LOOPBACK, BYPASS, RECEIVER ERROR MASK REGISTER (LBREMR) .................................................13
REGISTER 18 RX_ER COUNTER (REC) .....................................................................................................................14
REGISTER 19 SNR DISPLAY REGISTER.......................................................................................................................14
REGISTER 25 TEST REGISTER .....................................................................................................................................14
8. FUNCTIONAL DESCRIPTION.......................................................................................................................................15
8.1. MII AND MANAGEMENT INTERFACE ..........................................................................................................................15
8.1.1. Data Transition.....................................................................................................................................................15
8.1.2. Serial Management...............................................................................................................................................16
8.2. AUTO-NEGOTIATION AND PARALLEL DETECTION ......................................................................................................17
8.2.1. Setting the Medium Type and Interface Mode to MAC.........................................................................................17
8.2.2. UTP Mode and MII Interface ...............................................................................................................................18
8.2.3. UTP Mode and SNI Interface ...............................................................................................................................18
8.2.4. Fiber Mode and MII Interface..............................................................................................................................18
8.3. FLOW CONTROL SUPPORT ..........................................................................................................................................19
8.4. HARDWARE CONFIGURATION AND AUTO-NEGOTIATION ............................................................................................19
8.5. SERIAL NETWORK INTERFACE....................................................................................................................................20
8.6. POWER DOWN, LINK DOWN, POWER SAVING, AND ISOLATION MODES ......................................................................20
8.7. MEDIA INTERFACE .....................................................................................................................................................21
8.7.1. 100Base-TX Transmit & Receive Operation ........................................................................................................21
8.7.2. 100Base-FX Fiber Transmit & Receive Operation ..............................................................................................21
8.7.3. 10Base-T Transmit & Receive Operation .............................................................................................................22
8.8. REPEATER MODE OPERATION.....................................................................................................................................22
8.9. RESET, AND TRANSMIT BIAS ......................................................................................................................................22
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
iii
Rev. 1.1


3Pages


RTL8201N-GR 電子部品, 半導体
RTL8201N
Datasheet
List of Figures
Figure 1. Block Diagram .............................................................................................................................3
Figure 2. Pin Assignments...........................................................................................................................4
Figure 3. Read Cycle .................................................................................................................................16
Figure 4. Write Cycle ................................................................................................................................16
Figure 5. MII Transmission Cycle Timing-1.............................................................................................26
Figure 6. MII Transmission Cycle Timing-2.............................................................................................26
Figure 7. MII Reception Cycle Timing-1 ..................................................................................................27
Figure 8. MII Reception Cycle Timing-2 ..................................................................................................27
Figure 9. SNI Transmission Cycle Timing-1 ............................................................................................28
Figure 10. SNI Transmission Cycle Timing-2 ............................................................................................28
Figure 11. SNI Reception Cycle Timing-1..................................................................................................29
Figure 12. SNI Reception Cycle Timing-2..................................................................................................29
Figure 13. MDC/MDIO Timing ..................................................................................................................30
Figure 14. MDC/MDIO MAC to PHY Transmission Without Collision ...................................................30
Figure 15. MDC/MDIO PHY to MAC Reception Without Error ...............................................................31
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
vi
Rev. 1.1

6 Page



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部品番号部品説明メーカ
RTL8201N-GR

SINGLE-CHIP/PORT 10/100M FAST ETHERNET PHYCEIVER

REALTEK
REALTEK


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