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PDF ISL89160 Data sheet ( Hoja de datos )
| Número de pieza | ISL89160 | |
| Descripción | Power MOSFET Drivers | |
| Fabricantes | Intersil | |
| Logotipo |  |
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High Speed, Dual Channel, 6A, 4.5 to 16VOUT, Power
MOSFET Drivers
ISL89160, ISL89161, ISL89162
The ISL89160, ISL89161, and ISL89162 are high-speed, 6A,
dual channel MOSFET drivers. These parts are identical to the
ISL89163, ISL89164, ISL89165 drivers but without the enable
inputs for each channel.
Two input logic thresholds are available: 3.3V (CMOS and TTL
compatible) and 5.0V (CMOS).
Precision thresholds on all logic inputs allow the use of external
RC circuits to generate accurate and stable time delays on both
inputs, INA and INB. This capability is very useful for dead time
control.
At high switching frequencies, these MOSFET drivers use very
little bias current. Separate, non-overlapping drive circuits are
used to drive each CMOS output FET to prevent shoot-thru
currents in the output stage.
The start-up sequence is design to prevent unexpected glitches
when VDD is being turned on or turned off. When VDD < ~1V, an
internal 10kΩ resistor between the output and ground helps to
keep the output voltage low. When ~1V < VDD < UV, both outputs
are driven low with very low resistance and the logic inputs are
ignored. This insures that the driven FETs are off. When
VDD > UVLO, and after a short delay, the outputs now respond to
the logic inputs.
Features
• Dual output, 6A peak currents, can be paralleled
• Typical ON-resistance <1Ω
• Specified Miller plateau drive currents
• Very low thermal impedance (θJC = 3°C/W)
• Hysteretic input logic levels for 3.3V CMOS, 5V CMOS, and TTL
• Precision threshold inputs for time delays with external RC
components
• 20ns rise and fall time driving a 10nF load.
• NC pins may be connected to ground or VDD to ease PCB
layout difficulties.
Applications
• Synchronous Rectifier (SR) driver
• Switch mode power supplies
• Motor drives, class D amplifiers, UPS, inverters
• Pulse transformer driver
• Clock/line driver
Related Literature
• AN1603 “ISL6752/54EVAL1Z ZVS DC/DC Power Supply with
Synchronous Rectifiers User Guide”
NC
INA
GND
INB
1
2
3
4
EPAD
VDD
8 NC
7 OUTA
6
5 OUTB
4.7µF
FIGURE 1. TYPICAL APPLICATION
3.5
3.0 POSITIVE THRESHOLD
2.5
2.0
1.5 NEGATIVE THRESHOLD
1.0
0.5
0.0
-40 -25 10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
FIGURE 2. TEMPERATURE STABLE LOGIC THRESHOLDS
February 20, 2013
FN7719.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas LLC 2010-2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL89160, ISL89161, ISL89162
DC Electrical Specifications VDD = 12V, GND = 0V, No load on OUTA or OUTB, unless otherwise specified. Boldface limits apply over
the operating junction temperature range, -40°C to +125°C. (Continued)
PARAMETERS
SYMBOL
TEST CONDITIONS
TJ = +25°C
MIN TYP MAX
TJ = -40°C to +125°C
MIN
(Note 7)
MAX
(Note 7)
UNITS
Input Bias Current
for INA, INB
IIN GND < VIN < VDD
---
-10
+10 µA
OUTPUTS
High Level Output Voltage
VOHA VOHB
- - - VDD - 0.1 VDD
V
Low Level Output Voltage
VOLA VOLB
-
-
-
GND
GND + 0.1
V
Peak Output Source Current
IO VO (initial) = 0V, CLOAD = 10nF
- -6 -
-
-A
Peak Output Sink Current
IO VO (initial) = 12V, CLOAD = 10nF
- +6 -
-
-A
NOTES:
7. Compliance to data sheet limits is assured by one or more methods: production test, characterization and/or design.
8. This parameter is taken from the simulation models for the input FET. The actual capacitance on this input will be dominated by the PCB parasitic
capacitance.
9. A 400µs delay further inhibits the release of the output state when the UV positive going threshold is crossed. See Figure 9
10. The true state of a specific part number is defined by the input logic symbol.
11. The true state input voltage for the non-inverted inputs is greater than the Logic 1 threshold voltage. The true state input voltage for the inverted
inputs is less than the logic 0 threshold voltage.
AC Electrical Specifications VDD = 12V, GND = 0V, No Load on OUTA or OUTB, Unless Otherwise Specified. Boldface limits apply over
the operating junction temperature range, -40°C to +125°C.
PARAMETERS
SYMBOL
TJ = +25°C
TEST CONDITIONS MIN TYP MAX
TJ = -40°C to +125°C
MIN MAX
UNITS
Output Rise Time (see Figure 4)
tR CLOAD = 10nF,
10% to 90%
- 20 -
-
40 ns
Output Fall Time (see Figure 4)
tF CLOAD = 10nF,
90% to 10%
- 20 -
-
40 ns
Output Rising Edge Propagation Delay for
Non-Inverting Inputs (see Figure 3)
tRDLYn No load
- 25 -
-
50 ns
Output Rising Edge Propagation Delay with Inverting
Inputs (see Figure 3)
tRDLYi No load
- 25 -
-
50 ns
Output Falling Edge Propagation Delay with
Non-Inverting Inputs (see Figure 3)
tFDLYn No load
- 25 -
-
50 ns
Output Falling Edge Propagation Delay with Inverting
Inputs (see Figure 3)
tFDLYi No load
- 25 -
-
50 ns
Rising Propagation Matching (see Figure 3)
Falling Propagation Matching (see Figure 3)
Miller Plateau Sink Current
(See Test Circuit Figure 5)
tRM No load
tFM No load
-IMP VDD = 10V,
VMILLER = 5V
-IMP VDD = 10V,
VMILLER = 3V
-IMP VDD = 10V,
VMILLER = 2V
- <1 -
- <1 -
-6-
- 4.7 -
- 3.7 -
-
-
-
-
-
- ns
- ns
-A
-A
-A
5 FN7719.3
February 20, 2013
5 Page 
ISL89160, ISL89161, ISL89162
General EPAD Heatsinking
Considerations
The thermal pad is electrically connected to the GND supply
through the IC substrate. The epad of the ISL89160, ISL89161,
ISL89162 has two main functions: to provide a quiet GND for the
input threshold comparators and to provide heat sinking for the
IC. The EPAD must be connected to a ground plane and no
switching currents from the driven FET should pass through the
ground plane under the IC.
Figure 18 is a PCB layout example of how to use vias to remove
heat from the IC through the epad.
EPAD GND
PLANE
EPAD GND
PLANE
COMPONENT LAYER
BOTTOM
LAYER
FIGURE 18. TYPICAL PCB PATTERN FOR THERMAL VIAS
For maximum heatsinking, it is recommended that a ground
plane, connected to the EPAD, be added to both sides of the PCB.
A via array, within the area of the EPAD, will conduct heat from
the EPAD to the GND plane on the bottom layer. The number of
vias and the size of the GND planes required for adequate
heatsinking is determined by the power dissipated by the
ISL89160, ISL89161, ISL89162, the air flow and the maximum
temperature of the air around the IC.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11 FN7719.3
February 20, 2013
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ISL89160.PDF ] | |
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