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54LS173 PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 54LS173
部品説明 4-Bit D-Type Register
メーカ National Semiconductor
ロゴ National Semiconductor ロゴ 

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54LS173 Datasheet, 54LS173 PDF,ピン配置, 機能
May 1992
54LS173 DM74LS173A
TRI-STATE 4-Bit D-Type Register
General Description
This four-bit register contains D-type flip-flops with totem-
pole TRI-STATE outputs capable of driving highly capaci-
tive or low-impedance loads The high-impedance state and
increased high-logic-level drive provide these flip-flops with
the capability of driving the bus lines in a bus-organized sys-
tem without need for interface or pull-up components
Gated enable inputs are provided for controlling the entry of
data into the flip-flops When both data-enable inputs are
low data at the D inputs are loaded into their respective flip-
flops on the next positive transition of the buffered clock
input Gate output control inputs are also provided When
both are low the normal logic states of the four outputs are
available for driving the loads or bus lines The outputs are
disabled independently from the level of the clock by a high
logic level at either output control input The outputs then
present a high impedance and neither load nor drive the bus
line Detailed operation is given in the truth table
To minimize the possibility that two outputs will attempt to
take a common bus to opposite logic levels the output con-
trol circuitry is designed so that the average output disable
times are shorter than the average output enable times
Features
Y TRI-STATE outputs interface directly with system bus
Y Gated output control lines for enabling or disabling the
outputs
Y Fully independent clock eliminates restrictions for oper-
ating in one of two modes
Parallel load
Do nothing (hold)
Y For application as bus buffer registers
Connection Diagram
Function Table
Dual-In-Line Package
TL F 6403 – 1
Order Number 54LS173DMQB 54LS173FMQB
54LS173LMQB DM74LS173AM or DM74LS173AN
See NS Package Number E20A J16A
M16A N16E or W16A
Inputs
Clear Clock
Data
Enable
G1 G2
Data
D
Output
Q
HX X
XX
L
L L X X X Q0
uL H X X Q0
uL X H X Q0
LuL L L L
LuL
LHH
When either M or N (or both) is (are) high the output is
disabled to the high-impedance state however
sequential operation of the flip-flops is not affected
H e High Level (Steady State)
L e Low Level (Steady State)
u e Low-to-High Level Transition
X e Don’t Care (Any Input Including Transitions)
Q0 e The Level of Q Before the Indicated Steady State Input Conditions
Were Established
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 6403
RRD-B30M105 Printed in U S A

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