PDF ESS9018 Data sheet ( Hoja de datos )

Número de pieza	ESS9018
Descripción	Reference 32-bit Audio DAC
Fabricantes	ESS
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No Preview Available ! CONFIDENTIAL ADVANCE INFORMATION ES9012 / ES9018 Reference 32-bit Audio DAC ESS Technology, Inc. Datasheet OVERVIEW The SABRE32 Reference audio DAC series is the world’s highest performance 32-bit audio DAC solution targeted for consumer applications such as Blu-ray players, audio pre-amplifiers, A/V receivers and professional applications such as recording systems, mixer consoles and digital audio workstations. Part Description Package DNR (dB) THD (dB) 32-bit I2S/DSD SPDIF Jitter Number ES9018 SABRE32 Reference 64-LQFP 135 (mono) -120 DAC Yes Input Yes Input Reduction Yes Yes 8-Channel Audio DAC 129 (8ch) ES9012 SABRE32 Reference 64-LQFP 135 (mono) -120 Yes Yes Yes Yes Stereo Audio DAC 133 (2ch) With ESS patented 32-bit Hyperstream DAC architecture and Time Domain Jitter Eliminator, the SABRE32 Reference Stereo DAC delivers an unprecedented DNR of up to 135dB and THD+N of -120dB, the industry’s highest performance level that will satisfy the most demanding audio enthusiasts. The SABRE32 Reference audio DAC’s 32-bit Hyperstream architecture can handle full 32-bit PCM data via I2S input, as well as DSD or SPDIF data. The SABRE32 Reference supports up to 1.536MHz1 input sampling rates and consumes less than 100mW. KEY FEATURES Feature Patented 32-bit Hyperstream DAC o Up to 135dB DNR o -120dB THD+N Patented Time Domain Jitter Eliminator Universal digital input for up to 1.536MHz1 sampling rate Integrated DSP functions Customizable output configuration Customizable filter characteristics 100mW power consumption Benefit Industry’s highest performance 32-bit audio DAC with unprecedented dynamic range and ultra low distortion Unmatched audio clarity free from input clock jitter Supports SPDIF, PCM (I2S, MSB/LSB justified 16-32-bit) or DSD input with DVD Audio and SACD compatibility. Click-free soft mute and volume control Programmable filter characteristics for PCM/DSD Programmable Zero detect De-emphasis for 32, 44.1 and 48kHz sampling Mono, stereo, 8-channel (ES9018 only) output in current or voltage mode based on performance criterion User programmable filter allowing custom roll-off response Simplifies power supply design APPLICATIONS • Blu-ray / SACD / DVD-Audio player • Audio preamplifier and receiver • A/V processor • Professional audio recording systems and mixing consoles • Digital audio workstation 1. This is for oversample bypass mode only. The maximum sample rate using the internal oversampling filters is 500kHz. 1 Vista™ www.esstech.com High Definition 1 page Sabre32 Reference Datasheet February 11, 2010 CONFIDENTIAL ADVANCE INFORMATION Rev. 1.2 Pin Name I/O Description 40 AUTMOMUTE O Automute 41 ADDR I Chip Address Select 42 AVCC_R - Analog Power (+3.3V) for Right channels 43 AGND_R - Analog Ground for Right channels 44 DAC4 O Differential Positive Analog Output 4 45 DAC4B O Differential Negative Analog Output 4 46 DAC2B O Differential Negative Analog Output 2 47 DAC2 O Differential Positive Analog Output 2 48 VDD_R - Analog Power (+1.2V) for Right channels 49 AVCC_R - Analog Power (+3.3V) for Right channels 50 AGND_R - Analog Ground for Right channels 51 GND - Digital Ground 52 DATA8 I DSD Data8 OR SPDIF Input8 53 DATA7 I DSD Data7 OR SPDIF Input7 54 DATA6 I DSD Data6 OR SPDIF Input6 55 DATA5 I DSD Data5 OR PCM Data CH7/CH8 OR SPDIF Input5 56 DATA4 I DSD Data4 OR PCM Data CH5/CH6 OR SPDIF Input4 57 DATA3 I DSD Data3 OR PCM Data CH3/CH4 OR SPDIF Input3 58 DATA2 I DSD Data2 OR PCM Data CH1/CH2 OR SPDIF Input2 59 DATA1 I DSD Data1 OR PCM Frame Clock OR SPDIF Input1 60 DATA_CLK I PCM Bit Clock OR DSD Bit Clock 61 VDD - Digital Power (+1.2V) for core of chip 62 DVCC_T - Digital Power (+3.3V) for top pad ring of chip 63 AGND_L - Analog Ground for Left channels 64 AVCC_L - Analog Power (+3.3V) for Left channels Table 1.1 5 Vista™ www.esstech.com High Definition 5 Page Sabre32 Reference Datasheet February 11, 2010 CONFIDENTIAL ADVANCE INFORMATION Rev. 1.2 De-emphasis The de-emphasis feature is included for audio data that has utilized the 50/15uS pre-emphasis for noise reduction. There are 3 de-emphasis filters, one for 32 kHz, 44.1 kHz and 48 kHz. The de-emphasis filter can automatically be applied when an SPDIF stream sets the de-emphasis flag. It will auto detect the sample rate (32k, 44.1k, 48k) in either consumer or professional formats and then apply the correct de-emphasis filter. The automatic enabling of the de-emphasis filter can be disabled in Register 17 <en_auto>. OSF Bypass The oversampling FIR filter can be bypassed, sourcing data directly into the IIR filter. ESS recommends using 8Fs as the input. For example, an external signal at 44.1kHz can be oversampled externally to 844.1kHz = 352.8kHz and then applied to the serial decoder in either I2S, LJ or RJ format. The maximum sample rate that can be applied is 1.536MHz (8192kHz). SPDIF Data Select An SPDIF source multiplexer allows for up to eight SPDIF sources to be connected to the data pins on the SABRE32 Reference. The SABRE32 Reference uses an internal programmable register to select the appropriate data pin to decode. SPDIF input can be automatically decoded when there is valid SPDIF data if Register 17 <spdif_autodetect> is enabled. Programmable Filter The FIR filter can be programmed with custom coefficients to achieve an arbitrary frequency response that suits the needs of the product. The two stage interpolated filter exploits the symmetry of the coefficients to achieve a very sharp frequency response while using only 64 coefficients for the stage one filter and 14 coefficients for the stage two filter. Custom coefficients can be enabled via register 37 <prog_coeff_enabled> and can be programmed via the method explained in the FIR Programmable Filters section. The length of the stage 2 filter is configurable to either 27 or 28 coefficients via register 17 <fir_length>. System Clock (XI / MCLK) A system clock is required for proper operation of the digital filters and modulation circuitry. Maximum clock frequency is 100MHz. The system clock must also satisfy: Data Type DSD Data Serial Normal Mode Serial OSF Bypass Mode SPDIF Data Valid MCLK Frequencies 100MHz > MCLK > 3Fs , Fs = 2.8224MHz 100MHz > MCLK > 192Fs 100MHz > MCLK > 24Fs 100MHz > MCLK > 386Fs Data Clock DATA_CLOCK must be 64Fs for SERIAL, Fs for DSD modes, and is not required for SPDIF mode. This pin should be pulled low if not used. Built-in Digital Filters There are numerous applications for a stereo DAC so for added flexibility; two digital filter settings are possible, sharp roll-off and a slow roll-off for PCM mode. For DSD mode, there are 4 available filters with cutoffs at 47kHz, 50kHz, 60kHz, and 70kHz. 11 Vista™ www.esstech.com High Definition 11 Page

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