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PDF V260H1-LE1 Data sheet ( Hoja de datos )

Número de pieza V260H1-LE1
Descripción TFT LCD Module
Fabricantes CHI MEI 
Logotipo CHI MEI Logotipo



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No Preview Available ! V260H1-LE1 Hoja de datos, Descripción, Manual

Global LCD Panel Exchange Center
www.panelook.com
Issued Date: 30, Nov. 2010
Model No.: V260H1 Ω LE1
Approval
TFT LCD Approval Specification
MODEL NO.: V260H1- LE1
Customer:
Approved by:
Note:
Approved By
TV Product Marketing & Management Div
Chao-Chun Chung
Reviewed By
QA Dept.
Hsin-nan Chen
Product Development Div.
TC Pan
LCD TV Marketing and Product Management Div.
Prepared By
Vincent Chou
Delia Lin
1
Version 6.0
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V260H1-LE1 pdf
Global LCD Panel Exchange Center
www.panelook.com
Issued Date: 30, Nov. 2010
Model No.: V260H1 Ω LE1
Approval
1. GENERAL DESCRIPTION
1.1 OVERVIEW
V260H1- LE1 is a TFT Liquid Crystal Display module with LED Backlight unit and 2ch-LVDS interface. The
display diagonal is 26”. This module supports 1920 x 1080 Full HDTV format and can display 16.7M colors
(8-bit/color).
1.2 FEATURES
- Optimized Brightness 320nits
- Contrast Ratio 800:1
- Fast Response Time 5ms
- Color Saturation NTSC 72%
- Full HDTV (1920 x 1080 pixels) resolution, true HDTV format
- DE (Data Enable) Only Mode
- LVDS (Low Voltage Differential Signaling) Interface
- Viewing Angle: 160(H)/150(V) (CR>10) TN Technology
- Color Reproduction (Nature Color)
1.3 APPLICATION
-TFT LCD TVs
-Optimized Brightness, Multi-Media Displays
1.4 GENERAL SPECIFICATI0NS
Item
Active Area
Bezel Opening Area
Driver Element
Pixel Number
Pixel Pitch(Sub Pixel)
Pixel Arrangement
Display Colors
Display Operation Mode
Surface Treatment
Specification
576(H) x 324(V) (26.02” diagonal)
580.2(H) x 328.2 (V)
a-si TFT active matrix
1920x R.G.B. x 1080
0.100 (H) x 0.300 (V)
RGB vertical stripe
16.7M
Transmissive mode / Normally White
Anti-Glare coating (Haze 25%)
Hard Coating (3H)
Unit
mm
mm
-
pixel
mm
-
color
-
-
Note
(1)
-
-
-
-
-
-
(2)
1.5 MECHANICAL SPECIFICATIONS
Item
Horizontal (H)
Module Size Vertical (V)
Weight
Depth (D)
Weight
Min.
612
360
9.3
13.8
Typ.
613
361
10.3
14.8
2600
Max.
614
362
11.3
15.8
Unit Note
mm Module Size
mm
mm To Rear
mm To PCB Protector
g
Note (1)Please refer to the attached drawings for more information of front and back outline dimensions.
Note (2) Module Depth does not include connectors.
5
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V260H1-LE1 arduino
Global LCD Panel Exchange Center
www.panelook.com
Issued Date: 30, Nov. 2010
Model No.: V260H1 Ω LE1
Approval
5. INTERFACE PIN CONNECTION
5.1 TFT LCD MODULE
CNF1 Connector Pin Assignment
Pin Name
1 VCC
2 VCC
3 VCC
4 VCC
5 VCC
6 GND
7 GND
8 GND
9 GND
10 ORX0-
11 ORX0+
12 ORX1-
13 ORX1+
14 ORX2-
15 ORX2+
16 GND
17 OCLK-
18 OCLK+
19 GND
20 ORX3-
21 ORX3+
22 N.C.
23 N.C.
24 GND
25 ERX0-
26 ERX0+
27 ERX1-
28 ERX1+
29 ERX2-
30 ERX2+
31 GND
32 ECLK-
33 ECLK+
34 GND
35 ERX3-
36 ERX3+
37 N.C.
38 N.C.
39 GND
40 N.C.
41 N.C.
42 N.C.
43 N.C.
44 N.C.
45 SELLVDS
46 N.C.
47 N.C.
48 N.C.
49 N.C.
50 N.C.
51 N.C.
Description
+12V power supply
+12V power supply
+12V power supply
+12V power supply
+12V power supply
Ground
Ground
Ground
Ground
Odd pixel Negative LVDS differential data input. Channel 0
Odd pixel Positive LVDS differential data input. Channel 0
Odd pixel Negative LVDS differential data input. Channel 1
Odd pixel Positive LVDS differential data input. Channel 1
Odd pixel Negative LVDS differential data input. Channel 2
Odd pixel Positive LVDS differential data input. Channel 2
Ground
Odd pixel Negative LVDS differential clock input
Odd pixel Positive LVDS differential clock input.
Ground
Odd pixel Negative LVDS differential data input. Channel 3
Odd pixel Positive LVDS differential data input. Channel 3
No Connection
No Connection
Ground
Even pixel Negative LVDS differential data input. Channel 0
Even pixel Positive LVDS differential data input. Channel 0
Even pixel Negative LVDS differential data input. Channel 1
Even pixel Positive LVDS differential data input. Channel 1
Even pixel Negative LVDS differential data input. Channel 2
Even pixel Positive LVDS differential data input. Channel 2
Ground
Even pixel Negative LVDS differential clock input.
Even pixel Positive LVDS differential clock input.
Ground
Even pixel Negative LVDS differential data input. Channel 3
Even pixel Positive LVDS differential data input. Channel 3
No Connection
No Connection
Ground
No Connection
No Connection
No Connection
No Connection
No Connection
High(3.3V) or open for VESA, Low (GND) for JEIDA
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
Note
(1)
(1)
(1)
(3)
(1)
(1)
(1)
(3)
(3)
(4)(5)
(3)
11
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