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PDF ATS2503 Data sheet ( Hoja de datos )
| Número de pieza | ATS2503 | |
| Descripción | Third generation single-chip highly-integrated digital music system solution | |
| Fabricantes | Actions | |
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ATS2503 Datasheet
Latest Version: 1.1
2011-3-14
1 page  
ATS2503 Datasheet
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
5.3.10
5.3.11
5.3.12
DMA1 Destination Address 0 Register................................................................... 30
DMA1 Destination Address 1 Register................................................................... 30
DMA1 Destination Address 3 Register................................................................... 30
DMA1 DST Address Register ................................................................................... 31
DMA1 Byte Counter Low Register........................................................................... 31
DMA1 Byte Counter High Register .......................................................................... 31
DMA1 Mode Register ................................................................................................ 32
DMA1 Command Register ....................................................................................... 32
5.4 DMA Channel 2 .............................................................................................................. 33
5.4.1 DMA2 Source Address 0 Register........................................................................... 33
5.4.2 DMA2 Source Address 1 Register........................................................................... 33
5.4.3 DMA2 Source Address 3 Register........................................................................... 34
5.4.4 DMA2 SRC Address Register ................................................................................... 34
5.4.5 DMA2 Destination Address 0 Register................................................................... 34
5.4.6 DMA2 Destination Address 1 Register................................................................... 35
5.4.7 DMA2 Destination Address 3 Register................................................................... 35
5.4.8 DMA2 DST Address Register ................................................................................... 35
5.4.9 DMA2 Byte Counter Low Register........................................................................... 36
5.4.10 DMA2 Byte Counter High Register .......................................................................... 36
5.4.11 DMA2 Mode Register ................................................................................................ 36
5.4.12 DMA2 Command Register ....................................................................................... 37
5.5 CTC ................................................................................................................................... 38
5.5.1 CTC Prescale Register............................................................................................... 38
5.5.2 CTC T Period Low Register ....................................................................................... 39
5.5.3 CTC T Period High Register....................................................................................... 39
5.6 Interrupt Controller ........................................................................................................ 40
5.6.1 DMA/CTC IRQ Status Register................................................................................. 40
5.6.2 Master Interrupt Status Register............................................................................. 40
5.6.3 Master Interrupt Enable Register ............................................................................ 42
6 DSP ........................................................................................................................ 43
6.1 Description...................................................................................................................... 43
7 USB2.0 OTG........................................................................................................... 44
8 I2C Interface ......................................................................................................... 45
8.1 Description...................................................................................................................... 45
8.2 Register Description ...................................................................................................... 45
8.2.1 I2CADDR (I2C Address Register, 084h) ................................................................. 45
Copyright © Actions Semiconductor Co., Ltd. 2010. All rights reserved.
Version 1.0
Page 5
5 Page 
ATS2503 Datasheet
1 Overview
1.1 Introduction
ATS2503 is a third generation single-chip highly-integrated digital music system solution for
devices such as dedicated audio players. It includes a high performance dsp with embedded
RAM and ROM, ADPCM record capabilities and USB interface for downloading music and
uploading voice recordings. ATS2503 also provides an interface to SPDIF, flash memory,
LED/LCD, button and switch inputs, headphones, and microphone, and FM radio input and
control. It supports WMA and other digital audio standards. For devices like USB-Disk, it can
act as a USB mass storage slave device to personal computer system. The Chip has low
power consumption to allow long battery life, i.e. Li-on. The built-in Sigma-Delta D/A includes
a headphone driver to directly drive low impedance headphones. The A/D includes inputs for
both Microphone and Analog Audio in to support voice recording and FM radio integration
features. Thus, it provides a true ’ALL-IN-ONE’ solution that is ideally suited for highly
optimized digital audio players.
1.2 Features
z Support WMA Decoder and Other Digital Audio Standards
z Digital Voice Recording (ADPCM
z On-chip DSP data RAM1 6.25k*24bit, DSP data RAM2 4k*8bit and PCM RAM (8K*8bit)
that can be switched to be MCU memory space.
z Integrated MCU with DSU, the instruction set is compatible with Z80
z Internal ZRAM1 ((16K-64)*8bits), ZRAM2(1k*8bit), ZRAM3 ((8k+2k+192)*8bits)
accessed by MCU
z Internal BROM build in Boot up and USB Upgrade firmware
z Internal SRAM access time<7ns, MROM access time<16ns
z External Smart Media Card
z Support following memory card interface
.Multi Media Card Specification Version 4.2 (1/4/8 bit mode)
.Secure Digital Card Specification Version 2.0(1/4-bit mode)
.Memory Stick Version 1.43(1/4-bit mode)
.Memory Stick Pro Version 1.02(1/4-bit mode)
.Memory Stick Pro-HG Version 1.01(1/4/8-bit mode)
Copyright © Actions Semiconductor Co., Ltd. 2010. All rights reserved.
Version 1.0
Page 11
11 Page | ||
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