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ISL26102 の電気的特性と機能

ISL26102のメーカーはIntersilです、この部品の機能は「Low-Noise 24-bit Delta Sigma ADC」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL26102
部品説明 Low-Noise 24-bit Delta Sigma ADC
メーカ Intersil
ロゴ Intersil ロゴ 




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ISL26102 Datasheet, ISL26102 PDF,ピン配置, 機能
Low-Noise 24-bit Delta Sigma ADC
ISL26102, ISL26104
The ISL26102 and ISL26104 provide a low-noise
programmable gain amplifier along with a 24-bit Delta-Sigma
Analog-to-Digital Converter with two channel (ISL26102) or
four channel (ISL26104) differential, multiplexed inputs. The
devices feature exceptional noise performance for conversion
rates ranging from 2.5Sps to 4kSps.
The on-chip low-noise programmable-gain amplifier provides
gains ranging from 1 to 128, which supports ±19.5mVFS from
a 5V reference. The high input impedance allows direct
connection of sensors such as load cell bridges to ensure the
specified measurement accuracy without additional circuitry.
The Delta-Sigma ADC features a 3rd-order modulator providing
up to 21.5 bit noise-free performance (10Sps), with
user-selectable word rates. The converter can be operated
from an external clock source, an external crystal (typically
4.9152MHz), or the on-chip oscillator.
The ISL26102 and ISL26104 offer a simple-to-use serial
interface.
The ISL26102 and ISL26104 are available in a Thin Shrink
Small Outline Package (TSSOP). The devices are specified for
operation over the automotive temperature range (-40°C to
+105°C).
Features
• Programmable gain amplifier with gains of 1 to 128
• Low noise: 7nV/Hz @ PGA = 128
• Linearity error: 0.0002% FS
• Output word rates up to 4kSps
• Low-side switch for load cell power management
• +5V analog and +2.7V to +5V digital supplies
• ISL26102 in 24 Ld TSSOP
• ISL26104 in 28 Ld TSSOP
• ESD 7.5kV - HBM
Applications
• Weigh scales
• Temperature monitors and controls
• Load safety systems
• Industrial process control
• Pressure sensors
Related Literature
AN1704, “Precision Signal Path Data Acquisition System”
AVDD
ON-CHIP
TEMP
SENSOR
CAP
DVDD
DVDD
INTERNAL
CLOCK
EXTERNAL
OSCILLATOR
XTALIN/
CLOCK
XTALOUT
AIN1+
AIN1-
AIN2+
AIN2-
AIN3+
ISL26104 AIN3-
ONLY AIN4+
AIN4-
LSPS
INPUT
MULTIPLEXER
PGA
1, 2, 4, 8,16,
32, 64, 128
ΔΣ
ADC
CS
SDO/RDY
SDI
SCLK
PWDN
AGND
CAP DGND DGND VREF+ VREF- DGND DGND
FIGURE 1. BLOCK DIAGRAM
October 12, 2012
FN7608.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL26102 pdf, ピン配列
ISL26102, ISL26104
Pin Descriptions (TSSOP)
PIN NAME
DVDD
DGND
XTALIN/CLOCK
PIN NUMBER
ISL26102
ISL26104
1, 6 1, 6
2, 5, 7, 8
2, 5, 7, 8
33
XTALOUT
CAP
AIN1+
AIN1-
AIN3+
AIN3-
AIN4-
AIN4+
AIN2-
AIN2+
VREF-
VREF+
AGND
AVDD
LSPS
CS
SDI
PDWN
SCLK
SDO/RDY
4
9, 10
11
12
-
-
-
-
13
14
15
16
17
18
19
20
21
22
23
24
4
9, 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
ANALOG/DIGITAL
INPUT/OUTPUT
Digital
Digital
Digital/Digital Input
Digital
Analog
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Digital Output
Digital Input
Digital Input
Digital Input
Digital Input
Digital Output
DESCRIPTION
Digital Power Supply (2.7V to 5.25V)
Digital Ground
External Clock Input: Typically 4.9152MHz. Tie low
to activate internal oscillator. Can also use external
crystal across XTALIN/CLOCK and XTALOUT pins.
External Crystal Connection
PGA Filter Capacitor
Positive Analog Input Channel 1
Negative Analog Input Channel 1
Positive Analog Input Channel 3
Negative Analog Input Channel 3
Negative Analog Input Channel 4
Positive Analog Input Channel 4
Negative Analog Input Channel 2
Positive Analog Input Channel 2
Negative Reference Input
Positive Reference Input
Analog Ground
Analog Power Supply 4.75V to 5.25V
Low-Side Power Switch (Open Drain)
Chip Select (Active Low)
Serial Data Input
Device Power Down (Active Low)
Serial Port Clock
Data Ready signal (conversion complete) and
Serial Data Output
3 FN7608.0
October 12, 2012


3Pages


ISL26102 電子部品, 半導体
ISL26102, ISL26104
TABLE 1. INPUT REFERRED NOISE (nV, RMS)
OUTPUT WORD RATE
(Note 10)
PGA GAIN
1 2 4 8 16 32
2.5
187.1
101.8
52.0
25.0
14.5
8.8
5
209.2
112.2
55.9
28.5
16.3
10.5
10
253.6
133.0
63.8
35.5
20.0
13.9
20
308.3
157.7
77.6
43.8
25.0
18.1
40
417.7
207.1
105.1
60.2
35.1
25.3
80
547.2
264.6
140.1
78.2
46.8
34.9
100
607.0
292.7
159.4
87.5
52.2
39.7
160
780.3
368.2
203.0
110.6
68.0
52.3
200
845.1
405.5
222.2
119.7
74.2
57.3
320
1030.6
517.0
284.5
147.2
93.2
72.5
400
1169.0
591.7
318.1
165.3
105.2
81.9
640
1476.0
756.0
398.0
211.0
129.7
102.4
800
1632.0
857.9
445.0
237.2
139.5
114.7
1000
1806.1
958.6
489.5
267.0
157.8
126.8
1280
2018.0
1089.0
557.0
297.6
180.2
143.7
1600
2289.0
1234.0
632.0
328.0
202.3
163.4
2000
2572.5
1380.4
708.8
365.8
230.2
176.0
2560
2945.0
1538.0
801.0
423.7
259.0
201.0
3200
3287.0
1711.0
891.0
478.0
285.0
221.0
4000
3708.2
1876.9
955.1
545.1
316.6
242.8
NOTE:
10. The ADC has a programmable SINC4 filter. The -3dB bandwidth of the filter for a given word rate is 0.239 x OWR.
10000
64
6.6
8.4
11.9
15.7
23.3
31.6
35.4
46.2
50.6
64.1
72.6
90.2
101.0
112.4
124.3
134.0
147.6
162.3
178.0
196.0
128
6.5
8.2
11.6
15.2
22.4
30.1
34.3
45.2
49.5
62.5
70.5
87.4
98.9
107.7
123.5
132.0
145.8
161.3
174.3
194.9
1000
1X
100 2X
4X
8X
10
16X
32X
64X
128X
1
1 10 100 1000 10000
WORD RATE (Sps)
FIGURE 2. NOISE vs GAIN AND WORD RATE SETTINGS
6 FN7608.0
October 12, 2012

6 Page



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部品番号部品説明メーカ
ISL26102

Low-Noise 24-bit Delta Sigma ADC

Intersil
Intersil
ISL26104

Low-Noise 24-bit Delta Sigma ADC

Intersil
Intersil


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