|
|
PDF STA310 Data sheet ( Hoja de datos )
| Número de pieza | STA310 | |
| Descripción | MULTISTANDARD AUDIO DECODER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de STA310 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
STA310
6+2-CH. MULTISTANDARD AUDIO DECODER
PRELYMINARY DATA
1 FEATURES
s DVD Audio decoder:
Meridian Lossless Packing (MLP), with
up to 6 channels,
Uncompressed LPCM with 1-8 channels,
Precision of up to 24 bits and sample rates
of between 44.1 kHz and 192 kHz.
s Dolby Digital (*) decoder:
Decodes 5.1 Dolby Digital Surround.
Output up to 6 channels. downmix modes:
1, 2, 3 or 4 channels.
s MPEG -1 2- channel audio decoder, layers I and
II.
s MPEG-2 6-channel audio decoder, layer II.
24 bits decoding precision.
s MP3 (MPEG layer III) decoder.
s Accepts MPEG-2 PES stream format for:
MPEG-2, MPEG-1, Dolby Digital and linear
PCM.
s Karaoke System.
s Prologic decoder.
s Downmix for Dolby Prologic compatible.
A separate (2-ch) PCM output available for
simultaneous playing and recording.
s Bitstream input interface: serial, parallel or
SPDIF.
s SPDIF and IEC-61937 input interface.
s SPDIF and IEC-61937 output interface.
s PLL for internal PCM clock generation.
frequencies supported: 44.1KHz family (22.05,
88.2, 176.4) and 48KHz family (24, 48, 96, 192).
s PCM: transparent, downsampling 192 to 96 Khz
and 96 to 48kHz.
s PTS handling control on-chip.
s No external DRAM required
s I2C or parallel control bus
s Embedded Development RAM for
customizable software capability.
s Configurable internal PLLs for system and
audio clocks, from an externally provided clock.
s 80-PIN TQFP package
TQFP80
ORDERING NUMBER: STA310
s 2.5V (for core) and 3V (for I/O) power supply.
3V Capable I/O Pads .
s True-SPDIF input receiver supporting AES/
EBU, IEC958, S/PDIF.
No external chip required.
Differential or single ended inputs can be
decoded.
APPLICATIONS
s High-end audio equipment.
s DVD consumer players.
s Set top box.
s HDTV .
s Multimedia PC.
(*) “Dolby “, “AC-3” and “ProLogic” are
trademarks of Dolby Laboratories.
DESCRIPTION
The STA310 is a fully integrated Audio Decoder ca-
pable of decoding all the above listed formats.
Encoded input data can be entered either by a serial
(I2S or SPDIF) or a parallel interface. A second input
data stream (I2S) is available for micro input.
The control interface can be either I2C or a parallel 8-
bit interface. No external DRAM is necessary for a to-
tal of 35ms surround delays.
June 2003
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/90
1 page  
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameters
Vdd 2.5V Power Supply Voltage
2.5V Input or Output Voltage
Vdd3 3.3V Power Supply Voltage
3.3V Input or Output Voltage
STA310
Value
-0.5 to 3.3
-0.5 to (Vdd+0.5)
-0.5 to 4
-0.5 to (Vdd+0.5)
Unit
V
V
V
V
ELECTRICAL CHARACTERISTICS (VDD = 3.3V +/-0.3V; Tamb = 0 to 70°C; Rg = 50 Ω unless otherwise spec-
ified
DC OPERATING CONDITIONS
Symbol
Parameters
Value
Unit
Vcc Power Supply Voltage
2.5 V
Tj Operating Junction Temperature
-20 to 125
°C
GENERAL INTERFACE
Symbol
Parameters
Conditions
Min Typ Max Unit Note
Iil Low level input current without Vi = 0V
pull-up device
1 µA 1
Iih High level input current without Vi = Vdd
pull-down device
1 µA 1
Ioz Tri-state output leakage without Vi = 0V or Vdd
pull-up/down device
1 µA 1
Ilatchup I/O Latch-up current
V<0V, V>Vdd
200
mA 2
Vesd Electrostatic protection
Leakage <1µA
2000
V3
Note:
1. The leakage currents are generally very small, <1nA. The value given here, 1µA, is a maximum that can occur after an Electrostatic
Stress on the pin.
2. V> Vdd3 for 3.3V buffers.
3. Human Body Model
LVTTL & LVCMOS DC Input Specification 2.7V <Vdd3 <3.6V
Symbol
Parameters
Conditions
Min Typ Max Unit Note
Vil Low level input voltage
0.8 V
1
Vih High level input voltage
2.0 V 1
Vilhyst Low level threshold input falling
0.8
1.35 V
1
Vihhyst High level threshold input rising
1.3
2.0 V
1
Vhyst Schmitt trigger hysteresis
0.3
0.8 V
1
Note: 1. Takes into account 200mV voltage drop in both supply lines.
2. X in the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability
5/90
5 Page 
4.2 Clocks
There are two embedded PLLs in the STA310: the system PLL and the PCM PLL.
The following is the block diagram of the system and audio clocks used in the STA310
Figure 3. PLL Block Diagram
CLKOUT
CLK
RXN RXP
PCMCLK
STA310
/N
sys_clockout PLL Sys
PLL Audio
SPDIF
78
plls_config
sys_clk
DSP Core
pcm_clk
PCM_OUT
SCLOCK
LRCLK
PCMOUT0,1,2,3
Periph 1
R
Periph 2
Periph 3
IW
Figure 4. Block Diagram of Functional PLL
ClkIn
(27MHz)
DIV N+1
PFD
pll_disable
DIV M+1
dN
Frac
Switching
Circuit
update_frac
analog part
Charge Ip
Pump
VCO
Uvco
DIV (X+1)
Oclk
Filter (external)
R
C3 C
11/90
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet STA310.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| STA310 | MULTISTANDARD AUDIO DECODER | STMicroelectronics |
| STA312A | NPN General purpose |  Sanken |
| STA315A | Power Transistor Array | Sanken |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |