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HM624256ALJP-25のメーカーはHitachi Semiconductorです、この部品の機能は「262144-word x 4-bit High Speed CMOS Static RAM」です。 |
部品番号 | HM624256ALJP-25 |
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部品説明 | 262144-word x 4-bit High Speed CMOS Static RAM | ||
メーカ | Hitachi Semiconductor | ||
ロゴ | |||
このページの下部にプレビューとHM624256ALJP-25ダウンロード(pdfファイル)リンクがあります。 Total 12 pages
HM624256A Series
262144-word × 4-bit High Speed CMOS Static RAM
Rev. 0.0
Dec. 1, 1995
Description
The Hitachi HM624256A is a high speed 1M Static RAM organized as 262,144-word × 4-bit. It realizes
high speed access time (20/25/35 ns) and low power consumption, employing CMOS process technology
and high speed circuit designing technology. It is most advantageous for the field where high speed and
high density memory is required, such as the cache memory for main frame or 32-bit MPU. The
HM624256A, packaged in a 400-mil plastic SOJ is available for high density mounting.
Features
• Single 5 V supply and high density 28-pin package (DIP and SOJ)
• High speed
Access time: 20/25/35 ns (max)
• Low power dissipation
Active mode: 350 mW (typ)
Standby mode: 100 µW (typ)
• Completely static memory
No clock or timing strobe required
• Equal access and cycle time
• Directly TTL compatible
All inputs and outputs
1 Page Pin Arrangement
HM624256A Series
A0 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
A9 10
A10 11
CS 12
OE 13
VSS 14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
(Top view)
VCC
A17
A16
A15
A14
A13
A12
A11
NC
I/O 1
I/O 2
I/O 3
I/O 4
WE
Pin Description
Pin Name
A0 – A17
I/O1 – I/O4
CS
OE
WE
VCC
VSS
Function
Address
Input/output
Chip select
Output enable
Write enable
Power supply
Ground
3
3Pages HM624256A Series
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, unless otherwise noted.)
Test Conditions
• Input pulse levels: 0V to 3.0 V
• Input rise and fall time: 4 ns
• Input timing reference levels: 1.5 V
• Output timing reference levels: 1.5 V
• Output load: See figures
Dout
+5V
480 Ω
Dout
+5V
480 Ω
255 Ω
30 pF *1
255 Ω
5 pF *1
Output load (A)
Note: 1. Including scope and jig
Output load (B)
(For tCHZ, tOHZ, tCLZ, tOLZ, tWHZ and tOW)
Read Cycle
HM624256A-20 HM624256A-25 HM624256A-35
Parameter
Symbol Min Max Min Max Min Max Unit
Read cycle time
tRC 20 — 25 — 35 — ns
Address access time
tAA — 20 — 25 — 35 ns
Chip select access time
Chip selection to output in low-Z
tACS — 20 — 25 — 35 ns
t *1
CLZ
5
—5
—5
— ns
Output enable to output valid
tOE — 10 — 12 — 15 ns
Output enable to output in low-Z
t *1
OLZ
0
—0
—0
— ns
Chip deselection to output in high-Z
t *1
CHZ
0
10 0
12 0
15 ns
Chip disable to output in high-Z
t *1
OHZ
0
10 0
10 0
10 ns
Output hold from address change
t OH
5
—5
—5
— ns
Chip selection to power up time
tPU 0 — 0 — 0 — ns
Chip deselection to power down time tPD
— 12 — 15 — 25 ns
Notes: 1. Transition is measured ±200 mV from steady state voltage with Load (B). This parameter is
sampled not 100% tested.
6
6 Page | |||
ページ | 合計 : 12 ページ | ||
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PDF ダウンロード | [ HM624256ALJP-25 データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
HM624256ALJP-20 | 262144-word x 4-bit High Speed CMOS Static RAM | Hitachi Semiconductor |
HM624256ALJP-25 | 262144-word x 4-bit High Speed CMOS Static RAM | Hitachi Semiconductor |