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DM74S112のメーカーはFairchild Semiconductorです、この部品の機能は「Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop」です。 |
部品番号 | DM74S112 |
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部品説明 | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop | ||
メーカ | Fairchild Semiconductor | ||
ロゴ | |||
このページの下部にプレビューとDM74S112ダウンロード(pdfファイル)リンクがあります。 Total 4 pages
August 1986
Revised April 2000
DM74S112
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop
with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent negative-edge-trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flops on the falling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
negative going edge of the clock pulse. Data on the J and
K inputs can be changed while the clock is HIGH or LOW
without affecting the outputs as long as setup and hold
times are not violated. A low logic level on the preset or
clear inputs will set or reset the outputs regardless of the
logic levels of the other inputs.
Ordering Code:
Order Number Package Number
Package Description
DM74S112
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
Function Table
Inputs
Outputs
PR CLR CLK J K
Q
Q
L H X XX H
L
HL
X XX L
H
LL
X X X H*
H*
HH
HH
HH
HH
↓
LL
Q0
↓ HL H
Q0
L
↓ LH L
H
↓ HH
Toggle
HH
H X X Q0
Q0
H = HIGH Logic Level
X = Either LOW or HIGH Logic Level
L = LOW Logic Level
↓ = Negative going edge of pulse.
Q0 = The output logic level of Q before the indicated input conditions were
established.
* = This configuration is nonstable; that is, it will not persist when either the
preset and/or clear inputs return to its inactive (HIGH) level.
Toggle = Each output changes to the complement of its previous level on
each falling edge of the clock pulse.
© 2000 Fairchild Semiconductor Corporation DS006459
www.fairchildsemi.com
1 Page Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Typ
Min Max
(Note 6)
VI Input Clamp Voltage
VCC = Min, II = − 18 mA
VOH HIGH Level
VCC = Min, IOH = Max
Output Voltage
VIL = Max, VIH = Min
VOL LOW Level
VCC = Min, IOL = Max
Output Voltage
VIH = Min, VIL = Max
II Input Current @ Max Input Voltage VCC = Max, VI = 5.5V
IIH HIGH Level
VCC = Max
J, K
Input Current
VI = 2.7V
Clear
Preset
−1.2
2.7 3.4
0.5
1
50
100
100
Clock
100
IIL LOW Level
Input Current
VCC = Max
VI = 0.5V
(Note 7)
J, K
Clear
Preset
−1.6
−7
−7
Clock
−4
IOS Short Circuit Output Current
ICC Supply Current
Note 6: All typicals are at VCC = 5V, TA = 25°C.
VCC = Max (Note 8)
VCC = Max (Note 9)
−40 −100
30 50
Note 7: Clear is tested with preset HIGH and preset is tested with clear HIGH.
Note 8: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 9: With all outputs OPEN, ICC is measured with the Q and Q outputs HIGH in turn. At the time of measurement, the clock input is grounded.
Units
V
V
V
mA
µA
mA
mA
mA
Switching Characteristics
at VCC = 5V and TA = 25°C
Symbol
Parameter
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
From (Input)
To (Output)
Preset to Q
Preset to Q
Clear to Q
Clear to Q
Clock to Q or Q
Clock to Q or Q
RL = 280Ω
CL = 15 pF
CL = 50 pF
Min Max Min Max
80 60
79
7 12
79
7 12
79
7 12
Units
MHz
ns
ns
ns
ns
ns
ns
3 www.fairchildsemi.com
3Pages | |||
ページ | 合計 : 4 ページ | ||
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PDF ダウンロード | [ DM74S112 データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
DM74S11 | Triple 3-Input AND Gate | Fairchild Semiconductor |
DM74S112 | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop | Fairchild Semiconductor |