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25L6406E の電気的特性と機能

25L6406EのメーカーはMacronix Internationalです、この部品の機能は「MX25L6406E」です。


製品の詳細 ( Datasheet PDF )

部品番号 25L6406E
部品説明 MX25L6406E
メーカ Macronix International
ロゴ Macronix International ロゴ 




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25L6406E Datasheet, 25L6406E PDF,ピン配置, 機能
MX25L6406E
MX25L6406E
DATASHEET
P/N: PM1577
REV. 1.1, NOV. 17, 2010
1

1 Page





25L6406E pdf, ピン配列
MX25L6406E
POWER-ON STATE.................................................................................................................................................... 24
ELECTRICAL SPECIFICATIONS.............................................................................................................................. 25
ABSOLUTE MAXIMUM RATINGS...................................................................................................................... 25
Figure 3.Maximum Negative Overshoot Waveform............................................................................................ 25
CAPACITANCE TA = 25°C, f = 1.0 MHz............................................................................................................. 25
Figure 4. Maximum Positive Overshoot Waveform............................................................................................. 25
Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL.............................................................. 26
Figure 6. OUTPUT LOADING............................................................................................................................ 26
Table 8. DC CHARACTERISTICS...................................................................................................................... 27
Table 9. AC CHARACTERISTICS....................................................................................................................... 28
Timing Analysis......................................................................................................................................................... 29
Figure 7. Serial Input Timing............................................................................................................................... 29
Figure 8. Output Timing...................................................................................................................................... 29
Figure 9. Hold Timing.......................................................................................................................................... 30
Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1................................................ 30
Figure 11. Write Enable (WREN) Sequence (Command 06).............................................................................. 31
Figure 12. Write Disable (WRDI) Sequence (Command 04).............................................................................. 31
Figure 13. Read Status Register (RDSR) Sequence (Command 05)................................................................. 32
Figure 14. Write Status Register (WRSR) Sequence (Command 01)............................................................... 32
Figure 15. Read Data Bytes (READ) Sequence (Command 03)....................................................................... 32
Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B)................................................... 33
Figure 17. Dual Output Read Mode Sequence (Command 3B)......................................................................... 34
Figure 18. Sector Erase (SE) Sequence (Command 20)................................................................................... 34
Figure 19. Block Erase (BE) Sequence (Command 52 or D8).......................................................................... 34
Figure 20. Chip Erase (CE) Sequence (Command 60 or C7)............................................................................ 35
Figure 21. Page Program (PP) Sequence (Command 02)................................................................................ 35
Figure 22. Deep Power-down (DP) Sequence (Command B9)......................................................................... 36
Figure 23. Release from Deep Power-down (RDP) Sequence (Command AB)................................................ 36
Figure 24. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB).36
Figure 25. Read Identification (RDID) Sequence (Command 9F)...................................................................... 37
Figure 26. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90).............................. 37
Figure 27. Read Security Register (RDSCUR) Sequence (Command 2B)........................................................ 38
Figure 28. Write Security Register (WRSCUR) Sequence (Command 2F)........................................................ 38
Figure 29. Program/ Erase flow with read array data......................................................................................... 39
Figure 30. Power-up Timing................................................................................................................................ 40
Table 10. Power-Up Timing ................................................................................................................................ 40
OPERATING CONDITIONS....................................................................................................................................... 41
Figure 31. AC Timing at Device Power-Up......................................................................................................... 41
Figure 32. Power-Down Sequence..................................................................................................................... 42
P/N: PM1577
REV. 1.1, NOV. 17, 2010
3


3Pages


25L6406E 電子部品, 半導体
Status Register Feature
Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte device ID
- RES command for 1-byte Device ID
- REMS commands for 1-byte manufacturer ID and 1-byte device ID
HARDWARE FEATURES
• PACKAGE
- 16-pin SOP (300mil)
- 8-pin SOP (200mil)
- 8-land WSON (8x6mm)
- All Pb-free devices are RoHS Compliant
MX25L6406E
GENERAL DESCRIPTION
The device feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus.
The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access
to the device is enabled by CS# input.
When it is in Dual Output read mode, the SI and SO pins become SIO0 and SIO1 pins for data output.
The device provides sequential read operation on whole chip.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the speci-
fied page or sector/block locations will be executed. Program command is executed on byte basis, or page basis, or
word basis for erase command is executes on sector, or block, or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please see security features section for
more details.
When the device is not in operation and CS# is high, it is put in standby mode.
The device utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after typical
100,000 program and erase cycles.
P/N: PM1577
REV. 1.1, NOV. 17, 2010
6

6 Page



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部品番号部品説明メーカ
25L6406E

MX25L6406E

Macronix International
Macronix International


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