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45N03LTのメーカーはPhilips Semiconductorsです、この部品の機能は「PHP45N03LT」です。 |
部品番号 | 45N03LT |
| |
部品説明 | PHP45N03LT | ||
メーカ | Philips Semiconductors | ||
ロゴ | |||
このページの下部にプレビューと45N03LTダウンロード(pdfファイル)リンクがあります。 Total 8 pages
Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHP45N03LT
FEATURES
• ’Trench’ technology
• Very low on-state resistance
• Fast switching
• Stable off-state characteristics
• High thermal cycling performance
• Low thermal resistance
SYMBOL
g
d
s
QUICK REFERENCE DATA
VDSS = 30 V
ID = 45 A
RDS(ON) ≤ 24 mΩ (VGS = 5 V)
RDS(ON) ≤ 21 mΩ (VGS = 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode
logic level field-effect power
transistor in a plastic envelope
using ’trench’ technology. The
device has very low on-state
resistance. It is intended for use in
dc to dc converters and general
purpose switching applications.
The PHP45N03LT is supplied in the
SOT78 (TO220AB) conventional
leaded package.
PINNING
PIN DESCRIPTION
1 gate
2 drain
3 source
tab drain
SOT78 (TO220AB)
tab
1 23
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDS
VDGR
±VGS
ID
ID
IDM
Ptot
Tstg, Tj
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
-
RGS = 20 kΩ
-
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
-
THERMAL RESISTANCES
SYMBOL
Rth j-mb
Rth j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
-
in free air
MIN.
-
-
-
-
-
-
-
- 55
MAX.
30
30
15
45
36
180
86
175
UNIT
V
V
V
A
A
A
W
˚C
TYP.
-
60
MAX.
1.75
-
UNIT
K/W
K/W
November 1997
1
Rev 1.200
1 Page Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHP45N03LT
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
WDSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
CONDITIONS
ID = 25 A; VDD ≤ 25 V;
VGS = 10 V; RGS = 50 Ω; Tmb = 25 ˚C
MIN.
-
TYP.
-
MAX. UNIT
60 mJ
November 1997
3
Rev 1.200
3Pages Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHP45N03LT
VGS / V
5
4
VDS / V = 6
9528-30
24
3
2
1
0
0 5 10 15 20 25
QG / nC
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 40 A; parameter VDS
IF / A
60
9528-30
50
40
Tj / C = 175
25
30
20
10
0
0 0.5 1 1.5 2
VSDS / V
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
WDSS%
120
110
100
90
80
70
60
50
40
30
20
10
0
20 40 60 80 100 120 140 160 180
Tmb / C
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 25 A
VGS
0
RGS
L
VDS
T.U.T.
+ VDD
-
-ID/100
R 01
shunt
Fig.16. Avalanche energy test circuit.
WDSS = 0.5 ⋅ LID2 ⋅ BVDSS/(BVDSS − VDD)
+ VDD
RD
VGS
0
VDS
-
RG T.U.T.
Fig.17. Switching test circuit.
November 1997
6
Rev 1.200
6 Page | |||
ページ | 合計 : 8 ページ | ||
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部品番号 | 部品説明 | メーカ |
45N03LT | PHP45N03LT | Philips Semiconductors |
45N03LTG | P45N03LTG | Niko |