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PDF MGA-13116 Data sheet ( Hoja de datos )

Número de pieza MGA-13116
Descripción Very Low Noise Amplifier
Fabricantes Avago Technologies 
Logotipo Avago Technologies Logotipo



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MGA-13116
High Gain, High Linearity, Very Low Noise Amplifier
Data Sheet
Description
Avago Technologies’ MGA-13116 is a two stage, easy-to-
use GaAs MMIC Low Noise Amplifier (LNA). The LNA has
low noise with good input return loss and high linearity
achieved through the use of Avago Technologies’ propri-
etary 0.25 Pm GaAs Enhancement-mode pHEMT process.
Minimum matching needed for input, output and the
inter-stage between the two LNA.
It is designed for optimum use between 400 MHz to 1.5
GHz. For optimum performance at higher frequency from
1.5 GHz to 2.5 GHz, the MGA-13216 is recommended. Both
MGA-13116 & MGA-13216 share the same package and
pinout configuration.
Pin Configuration and Package Marking
4.0 x 4.0 x 0.85 mm3 16-lead QFN
AVAGO
13116
YYWW
XXXX
12
11
GND
10
9
Pin 2 Vbias
1 Pin 3 RFinQ1
Pin 10 RFoutQ2
2 Pin 11 RFoutQ2
3
Pin 13 RFinQ2
Pin 16 RFoutQ1
4
All other pics NC
Not Connected
Features
x Optimum frequency of operation 400 MHz – 1.5 GHz
x Very low noise figure
x High gain
x High linearity performance
x Excellent isolation
x GaAs E-pHEMT Technology[1]
x Low cost small package size: 4.0 x 4.0 x 0.85 mm3
Specifications
900 MHz; Q1: 5 V, 55 mA (typ) Q2: 5 V, 112 mA (typ)
x 0.51 dB Noise Figure
x 38 dB Gain
x 52 dB RFoutQ1 to RFinQ2 Isolation
x 41.4 dBm Output IP3
x 23.3 dBm Output Power at 1dB gain compression
Applications
x Low noise amplifier for cellular infrastructure including
GSM, CDMA, and W-CDMA.
x Other very low noise applications.
TOP VIEW
BOTTOM VIEW
Note:
Package marking provides orientation and identification
“13116” = Device Part Number
“YYWW” = Work Week and Year of Manufacture
“XXXX” = Lot Number
Attention: Observe precautions for
handling electrostatic sensitive devices.
ESD Machine Model = 90 V
ESD Human Body Model = 300 V
Refer to Avago Application Note A004R:
Electrostatic Discharge, Damage and Control.
Simplified Schematic
C9
R3
C8
Vdd1
C10
R4
R2
C7
L3
C6 R1
RFIN C1
L1
16 15
1
2 Q1bias
14 13
12
11
3 Q1
4
5
6
Q2 10
9
78
Vdd2
C5
C4
C3
L2
C2 RFOUT
Notes: Enhancement mode technology employs positive gate bias,
thereby eliminating the need of negative gate voltage associated with
conventional depletion mode devices.

1 page




MGA-13116 pdf
MGA-13116 Typical Performance in Demoboard for 900 MHz
TA = 25° C, Vdd1 = 5.0 V, Vdd2 = 5.0 V, Idd1 = 55 mA, Idd2 = 112 mA
1.2 45
85° C
1.0 25° C
-40° C
40
0.8
0.6 35
0.4
30
0.2
0.0
300 500 700 900 1100 1300 1500
Frequency (MHz)
Figure 9. NF vs Frequency and Temperature
25
300 500 700 900 1100
Frequency (MHz)
Figure 10. Gain vs Frequency and Temperature
85° C
25° C
-40° C
1300 1500
50
45
40
35
30
25
300 500 700 900 1100
Frequency (MHz)
Figure 11. OIP3 vs Frequency and Temperature
85° C
25° C
-40° C
1300 1500
28
26
24
22
20
18
16
300 500 700 900 1100
Frequency (MHz)
Figure 12. OP1dB vs Frequency and Temperature
85° C
25° C
-40° C
1300 1500
60
S11
40
S22
S21
S12
20
0
-20
-40
-60
012345
Frequency (GHz)
Figure 13. Input Return Loss, Output Return Loss, Gain, & Reverse Isolation
vs Frequency
10
9 85° C
8
25° C
-40° C
7
6
5
4
3
2
1
0
0 2 4 6 8 10 12 14 16 18 20
Frequency (GHz)
Figure 14. K-factor vs Frequency and Temperature
5

5 Page





MGA-13116 arduino
Reel Dimensions (7 inch reel)
SEE DETAIL "X"
6.25mm EMBOSSED LETTERS
LETTERING THICKNESS: 1.6mm
SLOT HOLE "b"
SLOT HOLE "a"
Ø178.0±0.5
FRONT
BACK
P6S
SLOT HOLE(2x)
180° APART.
6
PS
RECYCLE LOGO
FRONT VIEW
R10.65
R5.2
65° 45°
SLOT HOLE "a": 3.0±0.5mm(1x)
SLOT HOLE "b": 2.5±0.5mm(1x)
12.4 +1.5*
-0.0
1.5 MIN.
+0.5
Ø13.0 -0.2
Ø20.2 MIN.
FRONT
BACK
DETAIL "X"
3.5
DETAIL "Y"
(Slot Hole)
EMBOSSED RIBS
RAISED: 0.25mm, WIDTH: 1.25mm
BACK VIEW
Ø178.0±0.5
Ø51.2±0.3
SEE DETAIL "Y"
18.0*
MAX.
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved.
AV02-2877EN - December 19, 2011

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