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PDF SX19V007-ZZA Data sheet ( Hoja de datos )

Número de pieza SX19V007-ZZA
Descripción LCD Module
Fabricantes Hitachi 
Logotipo Hitachi Logotipo



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No Preview Available ! SX19V007-ZZA Hoja de datos, Descripción, Manual

Displays, Hitachi, Ltd.
3300 Hayano, Mobara City
Chiba Pref. 297 Japan
TEL : +81-475-25-9005 (Dial In)
FAX : +81-475-22-5217
For Messrs :
Date : Aug. 2, 2000
CUSTOMER'S ACCEPTANCE SPECIFICATIONS
SX19V007-ZZA
CONTENTS
No. ITEM
1 COVER
2 RECORD OF REVISIONS
3 GENERAL DATA
4 ABSOLUTE MAXIMUM RATINGS
5 ELECTRICAL CHARACTERISTICS
6 OPTICAL CHARACTERISTICS
7 BLOCK DIAGRAM
8 INTERFACE TIMING DIAGRAM
9 DIMENSIONAL OUTLINE
10 APPEARANCE STANDARD
11 PRECAUTION IN DESIGN
12 DESIGNATION OF LOT MARK
13 PRECAUTION FOR USE
Sheet No.
Page
3284PS 2701 -SX19V007-ZZA - 5
1-1/1
3284PS 2702 -SX19V007-ZZA - 5
2-1/1
3284PS 2703 -SX19V007-ZZA - 5
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3284PS 2704 -SX19V007-ZZA - 5
3284PS 2705 -SX19V007-ZZA - 5
3284PS 2706 -SX19V007-ZZA - 5
3284PS 2707 -SX19V007-ZZA - 5
3284PS 2708 -SX19V007-ZZA - 5
3284PS 2709 -SX19V007-ZZA - 5
3284PS 2710 -SX19V007-ZZA - 5
3284PS 2711 -SX19V007-ZZA - 5
3284PS 2712 -SX19V007-ZZA - 5
3284PS 2713 -SX19V007-ZZA - 5
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Accepted by :
Displays, Hitachi, Ltd.
Sh.
No.
Proposed by :
3284PS 2701 -SX19V007-ZZA - 5
Page 1-1/1

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SX19V007-ZZA pdf
5. ELECTRICAL CHARACTERISTICS
5. 1 ELECTRICAL CHARACTERISTICS OF LCD
ITEM
SYMBOL
CONDITION
VSS=0V
MIN
TYP
MAX UNIT
Pow er Supply Voltage
Contrast Adjustment
Voltage
(Note 1)
Input Voltage for Logic
Circuits
(Note 2)
VDD
VCON
Vi
VDD-VSS=3.3V
-
"H" level
"L" level
3.15
0.8
0.8VDD
0
3.30
-
-
-
3.45
2.8
VDD
0.2VDD
V
V
V
Pow er Supply Current
(Note 3)(Note 4)
IDD
Q
VDD-VSS=3.3V
CF
-
-
50 -
mA
80 120
Input Leak Current
Icon(Note5) Vcon=0.82.8V
Iin (Note2) Vin=VDDorVSS
-
-
- (20)
µA
- ±1.0
Contrast Adjustment
Voltage
(Note 6)
Frame Frequency
(Note 7)
Vcon
f FLM
Ta= 5°C, φ=0°
Ta=25°C, φ=0°
Ta=40°C, φ=0°
-
0.8 1.65
-
- 1.8 - V
- 1.95 2.8
80 100 120 Hz
(Note 1) The brightness w ill increase w ith decreasing contrast adjustment voltage.
(Note 2) DISPOFF, FLM, CL1, CL2, D0D7
(Note 3) fFLM=100Hz, Ta=25°C, "Q" test pattern(Q) and Checker pattern(CF) used as Display
pattern.
(Note 4) Rush Current at Pow er ON : 2A(PK) × 100µs
(Note 5) VCON
(Note 6) The Contrast Adjustment Voltage is specified as 1.8±0.3V under the condition, that
optimum contrast is obtained by naked eyes w ith a "Q" test pattern.
fFLM=100Hz, 1/497Duty
(Note 7) Please set the frame frequency so as to avoid flicker and rippling on the display.
(Note 8) The CFL cable has the follow ing absolute maximum ratings.
VCFL side : 2kV
VSS side : 300V
This CFL inverter shall not exceed the specified voltage.
(Note 9) Some points for attention w hile setting the driving condition of an appliance.
(1) Frame Frequency
Please set the frame frequency as the typical value (central value) w hich is show n in
CAS. According to the characteristic of response time of LC material, that setting the
frame frequency near the minimum value or under the minimum value show n in CAS w ill
cause a frame w ith moving phenomenon.
(2) Setting value of Vcon
Vcon, adjusted to get the best contrast ratio of LCD module, is adjusted to be distributed
w ithin the tolerance ±0.3V of central value in CAS before LCD modules ship the factory.
The below items are recommended at customer side.
(i) When designing the appliance, please set the Vcon value as an adjustable value.
(ii) And the Vcon value must be able to be adjusted to match the most suitable Vcon to
get the best contrast ratio. A fixed Vcon value is usually a little different from the
most suitable Vcon value of LCD module and causes a misjudgment.
(iii)The Vcon adjustment (w hen D/A [Digital/Analogue] converter is used) is
recommended to be set as 50mV at most per step. That one step is more than 50mV
may cause the input value to be not able to match the most suitable value.
The characteristic of contrast ratio can not present absolutely.
Dis p l a ys ,
Sh.
Hitachi, Ltd. Date Aug. 2, 2000 No.
3284PS 2705 -SX19V007-ZZA - 5
Page 5-1/3

5 Page





SX19V007-ZZA arduino
7. BLOCK DIAGRAM
CN3
FLM
CL1
CL2
DISPOFF
Buf f er
D7~D0
Buf f er
Timing M
Circuit
Timing
Circuit
DISPOFF
Column driv ing circuit
X1
Note1
TS1 Temperature
TS2 Sensor
VDD
VSS
VCON
DIG Y2
DIG X1
DIG Y1
DIG X2
Pow er
Supply
Circuit
LCD PANEL
X480
Y2
X1
Touch Panel
X2
Y1
VSS
VCFL
CN7
CFL
Note1; TDK NTCC20124CH104KCT
Dis p l a ys ,
Hitachi, Ltd. Date Aug. 2, 2000
Sh.
No.
3284PS 2707 -SX19V007-ZZA - 5
Page 7-1/1

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