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PDF MB91F592BS Data sheet ( Hoja de datos )
| Número de pieza | MB91F592BS | |
| Descripción | 32-bit Microcontroller | |
| Fabricantes | Fujitsu Media Devices | |
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FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
MN705-00009-3v0-E
FR81S
32-BIT MICROCONTROLLER
MB91590 Series
HARDWARE MANUAL
Following URL introduces the information for effective development of Fujitsu Semiconductor microcontrollers.
Helpful information is being released for the customers who are considering, or have adopted our
microcontrollers.
http://edevice.fujitsu.com/micom/en-support/
FUJITSU SEMICONDUCTOR LIMITED
1 page  
How to Use This Manual
MB91590 Series
Finding a function
The following methods can be used to search for the explanation of a desired function in this manual:
・Search from the table of the contents
The table of the contents lists the manual contents in the order of description.
・Search from the register
The register list for this device has been described. You can look up the name of a desired register on the
list to find the address of its location or the page that explains it.
The address where each register is located is not described in the text. To verify the address of a register,
see "B. I/O Map" of "APPENDIX".
・Search from the index
You can look up the keyword such as the name of a peripheral function in the index to find the
explanation of the function.
About the chapters
Basically, this manual explains 1 peripheral function per chapter.
Terminology
This manual uses the following terminology.
Term
Word
Half word
Byte
Explanation
Indicates access in units of 32 bits.
Indicates access in units of 16 bits.
Indicates access in units of 8 bits.
How to Read This Manual
・Primary Terms
The following explains the primary terms used in this series
Term
Explanation
A 32-bit width, high-speed internal bus.
The bus master is used for access from the CPU (for instruction fetch), the CPU (for
data reading or writing), or the on-chip bus.
XBS The bus slave is used to access to the on-chip bus, RAM (via the XBS built-in wild
register), and flash memory.
The bus has a crossbar switch configuration, and a circuit from each bus master to
each bus slave can operate simultaneously.
On-chip bus
A 32-bit width, high-speed internal bus. It has a 2-layer structure for XBS and DMA, and they
can operate simultaneously.
The bus master of the XBS layer is accessed from the XBS.
The bus master of the DMA layer is accessed from the DMA.
The bus slave of both layers has an external bus interface, CAN, 16/32-bit peripheral bus
bridge and others.
The bus slave of only DMA layer has an access to the XBS.
32-bit peripheral A 32-bit width, low-speed internal bus.
MN705-00009-3v0-E
FUJITSU SEMICONDUCTOR LIMITED
(5)
5 Page 
MB91590 Series
CONTENTS
CHAPTER 1: OVERVIEW..................................................................................................... 1
1. Overview ................................................................................................................................ 2
2. Features ................................................................................................................................. 3
2.1. FR81S CPU Core ................................................................................................................. 4
2.2. Peripheral Functions............................................................................................................. 5
3. Product Line-up...................................................................................................................... 8
4. Function Overview ............................................................................................................... 16
5. Block Diagram...................................................................................................................... 19
6. CPU...................................................................................................................................... 20
6.1. General-purpose Registers ................................................................................................ 21
6.2. Dedicated Registers ........................................................................................................... 22
7. Pin Assignment .................................................................................................................... 23
8. Package Dimensions ........................................................................................................... 25
9. Explanation of Pin Functions ............................................................................................... 27
10. Pins of Each Function........................................................................................................... 44
10.1. Pins of AD Converter .......................................................................................................... 45
10.2. Pins of CAN (ch.0 to ch.2) .................................................................................................. 46
10.3. Pins of External Interrupt Input (ch.0 to ch.15)................................................................... 47
10.4. Pins of LIN-UART (ch.2 to ch.7) ......................................................................................... 48
10.5. Pins of Multi-function Serial Interface (ch.0, ch.1).............................................................. 49
10.6. Pins of PPG (ch.0 to ch.23) ................................................................................................ 50
10.7. Pin of Real Time Clock ....................................................................................................... 52
10.8. Pins of Stepping Motor Controller (ch.0 to ch.5) ................................................................ 53
10.9. Pins of Output Compare (ch.0 to ch.3) ............................................................................... 54
10.10. Pins of Input Capture (ch.0 to ch.5) .................................................................................... 55
10.11. Pins of Sound Generator (ch.0 to ch.4)............................................................................... 56
10.12. Pins of Free-run Timer (ch.0, ch.1) ..................................................................................... 57
10.13. Pins of Base Timer (ch.0, ch.1) ........................................................................................... 58
10.14. Pins of Reload Timer (ch.0 to ch.3)..................................................................................... 59
10.15. Pins of External Bus Interface (GDC External Memory I/F)................................................ 60
10.16. Pins of SPI Interface (GDC External Memory I/F) .............................................................. 61
10.17. Pins of Port Function (General-purpose I/O) ...................................................................... 62
10.18. Pins of GDC (Capture RGB Mode) ..................................................................................... 65
10.19. Pins of GDC (Capture 656 Mode) ....................................................................................... 66
10.20. Pins of GDC (Capture Other) .............................................................................................. 67
10.21. Pins of GDC (Display) ......................................................................................................... 68
10.22. Pins of GDC (NTSC) ........................................................................................................... 69
10.23. Pin of GDC (Other).............................................................................................................. 70
10.24. Pins of Other ....................................................................................................................... 71
11. I/O Circuit Types ................................................................................................................. 72
CHAPTER 2: HANDLING THE DEVICE ..............................................................................77
1. Handling Precautions........................................................................................................... 78
2. Handling Device ................................................................................................................... 82
3. Application Notes ................................................................................................................. 85
3.1. Function Switching of a Multiplexed Port ........................................................................... 86
3.2. Low-power Consumption Mode.......................................................................................... 87
3.3. Notes When Writing Data in a Register Having the Status Flag ........................................ 88
MN705-00009-3v0-E
FUJITSU SEMICONDUCTOR LIMITED
( 11 )
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet MB91F592BS.PDF ] | |
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