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PDF MB91520 Data sheet ( Hoja de datos )
| Número de pieza | MB91520 | |
| Descripción | 32-bit Microcontroller | |
| Fabricantes | Spansion | |
| Logotipo |  |
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MB91520 Series
32-bit Microcontroller
FR Family FR81S
MB91F522B/D/F/J/K/L,MB91F523B/D/F/J/K/L,
MB91F524B/D/F/J/K/L,MB91F525B/D/F/J/K/L,MB91F526B/D/F/J/K/L*
Data Sheet (Full Production)
Publication Number MB91F526L_DS705-00011 Revision 2.0 Issue Date January 31, 2014
1 page  
DataSheet
· General-purpose ports:
MB91F52xB 44 sets (No sub oscillation), 42 sets (sub oscillation)
MB91F52xD 56 sets (No sub oscillation), 54 sets (sub oscillation)
MB91F52xF 76 sets (No sub oscillation), 74 sets (sub oscillation)
MB91F52xJ 96 sets (No sub oscillation), 94 sets (sub oscillation)
MB91F52xK 120 sets (No sub oscillation), 118 sets (sub oscillation)
MB91F52xL 152 sets (No sub oscillation), 150 sets (sub oscillation)
Included I2C open drain corresponding ports:16 sets
· External bus interface
· 22-bit address, 16-bit data
· DMA Controller
· Up to 16 channels can be started simultaneously.
· 2 transfer factors (Internal peripheral request and software)
· A/D converter (successive approximation type)
· 12-bit resolution : Max.48ch (32ch+16ch)
· Conversion time : 1μs
· D/A converter (R-2R type)
· 8-bit resolution : 2ch
· External interrupt input: 8 channels × 2 units total 16 channels
· Level ("H" / "L"), or edge detection (rising or falling) enabled
· Multi-function serial communication (built-in transmission/reception FIFO memory) : Max.12 channels
· 5V tolerant input: 4 channels ch.6, ch.8, ch.9, ch.11 CMOS hysteresis input
< UART (Asynchronous serial interface) >
· Full-duplex double buffering system, 64-step transmission FIFO memory, 64-step reception FIFO
memory
· Parity or no parity is selectable.
· Built-in dedicated baud rate generator
· An external clock can be used as the transfer clock
· Parity, frame, and overrun error detection functions provided
· DMA transfer support
<CSIO (Synchronous serial interface) >
· Full-duplex double buffering system, 64-step transmission FIFO memory, 64-step reception FIFO
memory
· SPI supported; master and slave systems supported; 5 to 16, 20, 24, 32-bit data length can be set.
· Built-in dedicated baud rate generator (Master operation)
· An external clock can be entered. (Slave operation)
· Overrun error detection function is provided
· DMA transfer support
· Serial chip select SPI function
<LIN (Asynchronous Serial Interface for LIN) >
· Full-duplex double buffering system, 64-step transmission FIFO memory, 64-step reception FIFO
memory
· LIN protocol revision 2.1 supported
· Master and slave systems supported
· Framing error and overrun error detection
· LIN synch break generation and detection; LIN synch delimiter generation
· Built-in dedicated baud rate generator
· An external clock can be adjusted by the reload counter
· DMA transfer support
· Hard assist function
< I2C >
· 2 channels ch.3 , ch.4 Standard mode/high-speed mode supported.
· 6 channels ch.5 to ch.8, ch.10, ch.11 Standard mode supported.
· Full-duplex double buffering system, 64-step transmission FIFO memory, 64-step reception FIFO
memory
· Standard mode (Max. 100kbps) / high-speed mode (Max. 400kbps) supported
· DMA transfer supported (for transmission only)
January 31, 2014, MB91F526L_DS705-00011-2v0-E
3
5 Page 
DataSheet
Product lineup comparison 144pins
MB91F522K MB91F523K MB91F524K MB91F525K MB91F526K
System Clock
Minimum instruction execution
time
Flash Capacity (Program)
Flash Capacity (Data)
RAM Capacity
External BUS I/F
(22address/16data/4cs)
DMA Transfer
16-bit Base Timer
Free-run Timer
Input capture
Output Compare
16-bit Reload Timer
PPG
Up/down Counter
Clock Supervisor
External Interrupt
A/D converter
D/A converter (8bit)
Multi-Function Serial Interface
CAN
Hardware Watchdog Timer
CRC Formation
Low-voltage detection reset
Flash Security
ECC Flash/WorkFlash
ECC RAM
Memory Protection Function
(MPU)
Floating point arithmetic (FPU)
Real Time Clock (RTC)
General-purpose port (#GPIOs)
SSCG
Sub clock
CR oscillator
NMI request function
OCD (On Chip Debug)
TPU (Timing Protection Unit)
Key code register
Waveform generator
Operation guaranteed temperature
(TA)
Power supply
Package
On chip PLL Clock multiple method
12.5ns (80MHz)
(256+64)KB (384+64)KB
(48+8)KB
(512+64)KB
64KB
(64+8)KB
(768+64)KB (1024+64)KB
(96+8)KB (128+8)KB
Yes
16ch
2ch
16bit×3ch
32bit×3ch
16bit×4ch
32bit×6ch
16bit×6ch
32bit×6ch
8ch
16bit×44ch
2ch
Yes
8ch×2units
12bit×32ch (1unit)
12bit×16ch (1unit)
2ch
12ch
64msg×2ch/128msg×1ch
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
120 ports
Yes
Yes
Yes
Yes
Yes
Yes
Yes
6ch
-40°C to +125°C
2.7V to 5.5V
LQFP-144
January 31, 2014, MB91F526L_DS705-00011-2v0-E
9
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MB91520.PDF ] | |
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