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PDF HCC4076B Data sheet ( Hoja de datos )
| Número de pieza | HCC4076B | |
| Descripción | 4 BIT D TYPE REGISTERS | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HCC4076B (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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. THREE STATE OUTPUTS
. INPUT DISABLE WITHOUT GATING THE
CLOCK
. GATED OUTPUT CONTROL LINES FOR EN-
ABLING OR DISABLING THE OUTPUTS
. QUIESCENT CURRENT SPECIFIED TO 20V
FOR HCC DEVICE
. 5V, 10V AND 15V PARAMETRIC RATINGS
. INPUT CURRENT OF 100nA AT 18V AND 25oC
FOR HCC DEVICE
. 100% TESTED FOR QUIESCENT CURRENT
. MEETS ALL REQUIREMENTS OF JEDECTEN-
TATIVE STANDARD N. 13A, ” STANDARD
SPECIFICATIONS FOR DESCRIPTION OF B
SERIES CMOS DEVICES ”
HCC4076B
HCF4076B
4 BIT D TYPE REGISTERS
EY
(Plastic Package)
F
(Ceramic Package)
M1
(Micro Package)
C1
(Chip Carrier)
ORDER CODES :
HCC4076BF
H CF 4076 BM 1
HCF4076BEY
H CF 4076 BC 1
DESCRIPTION
The HCC4076B (extended temperature range) and
HCC4076B (intermediate temperature range) are
monolithic integrated circuit, available in 16 lead
dual in line plastic or ceramic package and plastic
micropackage.
The HCC/HCF4076B types are four-bit registers
consisting of D-type flip-flops that feature three-
state outputs. Data Disable inputs are provided to
control the entry of data into theflip-flops. When both
Data Disable inputs are low, data at the D inputs are
loaded into their respective flip-flops on the next
positive transition of the click input. Output Disable
inputs are also provided. When the Output Disable
inputs are both low, the normal logic states of the
four outputs are available to the load. The outputs
are disabled independently of the clock by a high
logic level at either Output Disable input, and pres-
ent a high impedance.
September 1988
PIN CONNECTIONS
1/13
1 page  
HCC/HCF4076B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25 oC, CL = 50 pF, RL = 200 KΩ,
typical temperature coefficent for all VDD values is 03 %/oC, all input rise and fall times= 20 ns)
Symbol
Parameter
tPLH Propagation Delay Time
tPHL (Clock to Q Output)
tPHL(R) Propagation Delay Time
(Reset)
tP(1-H)
tP(0-H)
3-State Output 1 or 0 to High Impedance
tP(H-1) 3-State High Impedance to 1 or 0 Output
tP(L-1)
tW Clock Pulse Width
tW Reset Pulse Width
tsetup Data Setup Time
tsetup Data Input Disable Setup Time
fmax Maximum Clock Frequency
tr, tf Clock Input Rise or Fall Time
Test Conditions
VDD (V)
5
10
15
5
10
15
RL = 1KΩ
5
10
15
RL = 1KΩ
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
Min.
200
100
80
120
50
40
200
80
60
180
100
70
3
6
8
15
5
5
Value
Typ.
300
125
90
230
100
75
150
75
60
150
75
60
100
50
40
60
25
20
100
40
30
90
50
35
6
12
16
Max.
600
250
180
460
200
150
300
150
120
300
150
120
Unit
ns
ns
ns
ns
ns
ns
ns
ns
MHz
µs
5/13
5 Page 
DIM.
A
a1
a2
b
b1
C
c1
D
E
e
e3
F
G
L
M
S
HCC/HCF4076B
SO16 (Narrow) MECHANICAL DATA
MIN.
0.1
0.35
0.19
9.8
5.8
3.8
4.6
0.5
mm
TYP.
0.5
1.27
8.89
MAX.
1.75
0.2
1.65
0.46
0.25
MIN.
0.004
0.013
0.007
45° (typ.)
10 0.385
6.2 0.228
4.0 0.149
5.3 0.181
1.27 0.019
0.62
8° (max.)
inch
TYP.
0.019
0.050
0.350
MAX.
0.068
0.007
0.064
0.018
0.010
0.393
0.244
0.157
0.208
0.050
0.024
P013H
11/13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet HCC4076B.PDF ] | |
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