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Número de pieza | T-55313D141J-LW-A-AGN | |
Descripción | WXGA Display Module | |
Fabricantes | Optrex | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de T-55313D141J-LW-A-AGN (archivo pdf) en la parte inferior de esta página. Total 26 Páginas | ||
No Preview Available ! TENTATIVE
All information in this technical data sheet is tentative
and subject to change without notice.
Preliminary
14.1” WXGA
TECHNICAL SPECIFICATION
T-55313D141J-LW-A-AGN
OPTREX CORPORATION
Date: Jun.24,’10
OPTREX Confidential
(1/26)
T-55313D141J-LW-A-AGN_02_00
1 page 3. ABSOLUTE MAXIMUM RATINGS
ITEM
SYMBOL
MIN.
MAX
UNIT
Power Supply Voltage for LCD
VCC
0
4.0 V
Logic Input Voltage
VI 0.3 VCC0.3 V
Backlight (LED) Current
IF 0 180 mA
Operation Temperature(Panel)
Note 1,2)
Top(Panel)
20
70 °C
Operation Temperature(Ambient) Note 2)
Top(Ambient)
20
70 °C
Storage Temperature
Note 2)
Tstg
20
80 °C
[Note]
1) Measured at the center of active area and at the center of panel back surface
2) Top,Tstg 40C : 90%RH max. without condensation
Top,Tstg > 40C : Absolute humidity shall be less than the value of 90%RH at 40C without
condensation.
4. ELECTRICAL CHARACTERISTICS
(1) TFT-LCD
ITEM
SYMBOL MIN.
Power Supply Voltages for LCD VCC
3.0
Power Supply Currents for LCD ICC
--
Permissive Input Ripple Voltage VRP
--
Logic Input Voltage
High
Low
VIH 0.8VCC
VIL 0
*1) Power and signals sequence:
t1 10ms
0 < t2 50 ms
0 < t3 50 ms
200 ms t4
200 ms t5
0 t6
TYP.
3.3
570
--
--
--
Ambient temperature: Ta = 25°C
MAX. UNIT
Remarks
3.6 V
*1)
960 mA
*2)
100 mVp-p VCC = +3.3V
VCC
V
MODE
0.2VCC V
MODE
LCD Power Supply
0.9VCC
Logic Signal
0.1VCC
VCC
data
0.9VCC
0.1VCC 0.1VCC
t1 t2
t3 t4
Backlight Power Supply
t5 t6
data: RGB DATA, DCLK, DENA, MODE
OPTREX Confidential
(5/26)
T-55313D141J-LW-A-AGN_02_00
5 Page 6. INTERFACE TIMING
LVDS transmitter input signal
(1) Timing Specifications
ITEM
SYMBOL MIN
TYP
MAX
UNIT
DCLK
DENA
Frequency
Period
Active Time
Blanking Time
Horizontal
Frequency
Period
Active Time
Vertical
Blanking Time
Frequency
fCLK
tCLK
tHA
tHB
fH
tH
tVA
tVB
fV
50
12.5
1280
20
42.4
16.6
800
3
55
71
14.1
1280
160
49.4
20.3
800
23
60
80
20
1280
--
60
23.6
800
--
70
MHz
ns
tCLK
tCLK
kHz
s
tH
tH
Hz
Period
tV 14.3 16.7 18.2 ms
[Note]
1) DENA (Data Enable) should always be positive polarity as shown in the timing specification.
2) DCLK should appear during all invalid period.
3) LVDS timing follows the timing specifications of LVDS receiver IC: THC63LVDF84B(Thine).
4) In case of blanking time fluctuation, please satisfy following condition.
tVBn > tVBn-1 3(tH)
OPTREX Confidential
(11/26)
T-55313D141J-LW-A-AGN_02_00
11 Page |
Páginas | Total 26 Páginas | |
PDF Descargar | [ Datasheet T-55313D141J-LW-A-AGN.PDF ] |
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