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PDF STMIPID02 Data sheet ( Hoja de datos )
| Número de pieza | STMIPID02 | |
| Descripción | Dual mode MIPI CSI-2 / SMIA CCP2 de-serializer | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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STMIPID02
Dual mode MIPI CSI-2 / SMIA CCP2 de-serializer
Features
■ Dual mode camera de-serializer
■ MIPI CSI-2 receivers (Rev.0.9 compliant)
– Two camera interfaces support
– One 1.6Gbps dual data lane receiver for
main camera with selectable 1/2 lane
operation
– One 800Mbps single data lane receiver for
second camera
– Each MIPI D-PHY interface with a 400MHz
DDR clock lane
– MIPI D-PHY Pass through mode
■ SMIA CCP2 receivers
– Two camera interfaces support
– 650Mbps class 2 receivers with selectable
data/clock and data/strobe operation
■ Support for MIPI CSI-2 and SMIA CCP2
RAW6, RAW7, RAW8 (Generic), RAW10 and
RAW12 Raw Bayer format data unpacking
■ Support for YUV, RGB and JPEG formats
■ Support for SMIA 8-10, 7-10, 6-10, 8-12, 7-12
& 6-12 DPCM/PCM decompression options
■ 1V8, 200MHz,12-bit parallel output interface
■ HSYNC, VSYNC and continuous PCLK output
data qualification signal
■ Tristate-able output for dual camera systems
■ Error interrupt output (D-PHY and protocol)
■ MIPI CSI-2 short packet interrupt output
■ 2-wires 100/400 kHz control interface
(I2C compatible slave) to configure D-PHY
timeouts and pixel data
unpacking/decompression options
■ Integrated power-on-reset cell
■ Digital power supply: 1.7V to 1.9V
■ Integrated 1.2V regulator for D-PHY and core
logic
■ VFBGA 49pin 3.0mm x 3.0mm x1.0mm F7x7
0.4mm pitch, 0.25mm ball package
■ Lead-free RoHS compliant product
Description
The STMIPID02 is a dual mode MIPI CSI-2 /
SMIA CCP2 de-serializer targeted at mobile
camera phone applications. Manufactured using
ST 65nm process, it integrates two MIPI CSI-2 /
SMIA CCP2 receivers. The STMIPID02 can then
support the main and the second cameras of a
mobile camera phone.
One of the two MIPI CSI-2 receivers is a dual lane
receiver allowing to connect high resolution / high
frame rate cameras.
The SMIA CCP2 compatible receivers share the
same input pins as the MIPI CSI-2 receivers.
STMIPID02’s 12-bit parallel output interface is
capable of outputting de-serialized pixel data at
rates up to 200MHz.
Pass through mode allows STMIPID02 to be used
as a standalone MIPI D-PHY physical layer
device.
With this device an host with a standard 8-bit, 10-
bit or 12-bit parallel input interface can be
connected to camera modules with either a MIPI
CSI-2 or a SMIA CCP2 low voltage, fully
differential bit-serial, low EMI interface.
An interrupt output for every MIPI CSI-2 short
packet.
Power management is simplified by the presence
of an integrated 1.2V regulator to supply the MIPI
D-PHY receiver and core logic.
STMIPID02 is fully configurable via an I2C
compatible slave control I/F.
March 2009
Draft Rev 0.7
For further information contact your local STMicroelectronics sales office.
1/52
www.st.com
52
1 page  
STMIPID02
Output video port
Figure 5. 12-bit parallel data interface signals - Frame level
1 line
PCLK
D[11:0]
0x01C
L0 L1 L2 L3
LN-4 LN-3 LN-2 LN-1 0x01C
HSYNC
VSYNC
Figure 6. 12-bit parallel data interface signals - Line level
First line:
1 pixel
PCLK
D[11:0]
0x01C
P0 P1 P2 P3
PN-4 PN-3 PN-2 PN-1
0x01C
HSYNC
VSYNC
Last line:
PCLK
D[11:0]
HSYNC
VSYNC
0x01C
P0 P1 P2 P3
PN-4 PN-3 PN-2 PN-1 0x01C
Draft Rev 0.7
5/52
5 Page 
STMIPID02
8 Functional Description
8.1 Power-up sequence
Please find below the timing of Power up sequence
Figure 9. Power-up sequence
VDDIN_LDO
XSDN
T1
Functional Description
EXTCLK
VDDOUT_LDO
T2
T3
POR_SGN
Table 3. Power-up sequence timing
Symbol
Parameter
Min.
T1 Time between Power-up and LDO VDDIN_LDO
enable
stable
T2
Time between XSDN & CORE power
up (LDO out rise to 1.2V)
T3
Time between CORE power up to
1.2V & reset generation
Typ.
20
Max.
+inf
5
Unit
s
ms
µs
Draft Rev 0.7
11/52
11 Page | ||
| Páginas | Total 52 Páginas | |
| PDF Descargar | [ Datasheet STMIPID02.PDF ] | |
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