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HCC4029B の電気的特性と機能

HCC4029BのメーカーはSTMicroelectronicsです、この部品の機能は「BINARY OR BCD DECADE PRESETTABLE UP/DOWN COUNTER」です。


製品の詳細 ( Datasheet PDF )

部品番号 HCC4029B
部品説明 BINARY OR BCD DECADE PRESETTABLE UP/DOWN COUNTER
メーカ STMicroelectronics
ロゴ STMicroelectronics ロゴ 




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HCC4029B Datasheet, HCC4029B PDF,ピン配置, 機能
HCC4029B
HCF4029B
PRESETTABLE UP/DOWN COUNTER
BINARY OR BCD DECADE
. MEDIUM SPEED OPERATION - 8MHz (typ.) @
CL = 50pF AND VDD-VSS = 10V
. MULTI-PACKAGE PARALLEL CLOCKING FOR
SYNCHRONOUS HIGH SPEED OUTPUT RES-
PONSE OR RIPPLE CLOCKING FOR SLOW
CLOCK INPUT RISE AND FALL TIMES
. ”PRESET ENABLE” AND INDIVIDUAL ”JAM”
INPUTS PROVIDED
. BINARY OR DECADE UP/DOWN COUNTING
. BCD OUTPUTS IN DECADE MODE
. STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
. 5V, 10V, AND 15V PARAMETRIC RATINGS
. INPUT CURRENT OF 100nA AT 18V AND 25°C
FOR HCC DEVICE
. QUIESCENT CURRENT SPECIFIED TO 20V
FOR HCC DEVICE
. 100% TESTED FOR QUIESCENT CURRENT
. MEETS ALL REQUIREMENTS OF JEDECTEN-
TATIVE STANDARD No. 13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIES CMOS DEVICES”
EY
(Plastic Package)
F
(Ceramic Package)
M1
(Micro Package)
C1
(Chip Carrier)
ORDER CODES :
HCC4029BF
H CF 4029 BM 1
HCF4029BEY
H CF 4029 BC 1
DESCRIPTION
The HCC4029B (extended temperature range) and
HCF4029B (intermediate temperature range) are
monolithic integrated circuit, available in 16-lead
dual in-line plastic or ceramic package and plastic
micro package. The HCC/HCF4029B consists of a
four-stage binary or BCD-decade up/down counter
with provisions for look-ahead carry in both counting
modes. The inputs consist of a single CLOCK,
CARRY-IN (CLOCK ENABLE), BINARY/DECADE,
UP/DOWN, PRESET ENABLE, and four individual
JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT
signal are provided as outputs. A high PRESET EN-
ABLE signal allows information on the JAM INPUTS
to preset the counter to any state asynchronously
with the clock. A low on each JAM line, when the
PRESET-ENABLE signal is high, resets the counter
to its zero count. The counter is advanced one count
at the positive transition of the clock when the
CARRY-IN and PRESET ENABLE signals, are low.
Advancement is inhibited when the CARRY-IN or
PRESET ENABLE signals are high. The CARRY-
OUT signal is normally high and goes low when the
PIN CONNECTIONS
NC = No Internal Connection
September 1988
1/13

1 Page





HCC4029B pdf, ピン配列
RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
VI
Top
Parameter
Supply Voltage: HCC Types
HCF Types
Input Voltage
Operating Temperature: HCC Types
HCF Types
LOGIC DIAGRAMS
HCC/HCF4029B
Value
3 to 18
3 to 15
0 to VDD
-55 to +125
-40 to +85
Unit
V
V
V
oC
oC
TRUTH TABLES
CLOCK TE
XX
O
XX
I
X
X DON’T CARE
PE
O
I
O
I
I
J
O
X
I
X
X
QQ
OI
QQ
IO
Q Q NC
Q Q NC
Control Input
BIN/DEC
(B/D)
UP/DOWN
(U/D)
Preset Enable
(PE)
Carry In (Cl)
(Clock Enable)
Logic Level
Action
I Binary Count
O Decade Count
I Up Count
O Down Count
I Jam In
O No Jam
No Counter
I Advance at Pos.
Clock Transition
Advance Counter
O at Pos. Clock
Transition
3/13


3Pages


HCC4029B 電子部品, 半導体
HCC/HCF4029B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25 oC, CL = 50 pF, RL = 200 K,
typical temperature coefficent for all VDD values is 03 %/oC, all input rise and fall times= 20 ns)
Symbol
Parameter
Test Conditions
Value
Unit
VDD (V) Min. Typ. Max.
tPLH Propagation Delay Time (Q Outputs)
tPHL
5 250 500
10
120 240
ns
15 90 180
tPLH Propagation Delay Time (Carry Output)
tPHL
5 280 560
10
130 260
ns
15 95 190
tTLH Transition Time (Q Outputs, Carry Output)
tTHL
5 100 200
10
50 100
ns
15 40 80
tW Minimum Clock Pulse Width
5 90 180
10
45 90
ns
15 30 60
tr, tf ** Clock Rise and Fall Time
5 15
10 15 µs
15 15
tsetup * Minimum Setup Time (Carry Input)
5 30 60
10 10 20
tsetup Minimum Setup Time (B/D or UD)
15
6 12
ns
5 170 340
10 70 140
15 50 100
fmax Maximum Clock Input Frequency
5 24
10 4 8
MHz
15 5.5 11
PRESET ENABLE
tPLH Propagation Delay Time (Q Outputs)
tPHL
5 235 470
10 100 200
tPLH Propagation Delay Time (Carry Output)
tPHL
15
80 160
ns
5 320 640
10 145 290
15 105 210
tW Minimum Preset Enable (Pulse Width)
5 65 130
10
35 70
ns
15 25 50
trem * Minimum Preset Enable (Removal Time)
5 100 200
10 55 110 ns
15 40 80
CARRY INPUT
tPHL Propagation Delay Time (Carry Output)
tPLH
5 170 340
10 70 140 ns
15 50 100
tsetup *** Minimum Setup Time (Carry In)
5 25 50
10 15 30
thold Minimum Hold Time (Carry In)
15
12 25
ns
5 100 200
10 35 70
* From Up/Down, Binary/Decade, Carry In or Preset Enable Control Inputs to Clock Edge
15
30 60
** If more than one unit is cascated in the parallel clocked application tr should be made less than or equal to the sum of the fixed propagation
delay at 15 pF and the transition time of the carry output driving stage for the estimated capacitance load.
*** From Carry in to Clock Edge.
6/13

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
HCC4029B

BINARY OR BCD DECADE PRESETTABLE UP/DOWN COUNTER

STMicroelectronics
STMicroelectronics
HCC4029BF

BINARY OR BCD DECADE PRESETTABLE UP/DOWN COUNTER

STMicroelectronics
STMicroelectronics


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