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PDF HCC4018 Data sheet ( Hoja de datos )
| Número de pieza | HCC4018 | |
| Descripción | PRESETTABLE DIVIDE-BY-N COUNTER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HCC4018 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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HCC/HCF4018B
PRESETTABLE DIVIDE-BY-N COUNTER
. MEDIUM SPEED OPERATION - 10MHz (typ.)
AT VDD – VSS = 10V
. FULLY STATIC OPERATION
. QUIESCENT CURRENT SPECIFIED TO 20V
FOR HCC DEVICE
. STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
. INPUT CURRENT OF 100nA AT 18V AND 25°C
FOR HCC DEVICE
. 100% TESTED FOR QUIESCENT CURRENT
. 5V, 10V, AND 15V PARAMETRIC RATINGS
. MEETS ALL REQUIREMENTS OF JEDECTEN-
TATIVE STANDARD No 13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIES CMOS DEVICES”
EY
(Plastic Package)
F
(Ceramic Frit Seal Package)
M1
(Micro Package)
C1
(Plastic Chip Carrier)
ORDER CODES :
HCC4018BF HCF4018BM1
HCF4018BEY HCF4018BC1
DESCRIPTION
The HCC4018B (extended temperature range) and
HCF4018B (intermediate temperature range) are
monolithic integrated circuit, available in 16-lead
dual in-line plastic or ceramic package and plastic
micropackage.
The HCC/HCF4018B types consist of 5 Johnson-
Counter stages, buffered Q outputs from each
stage, and counter preset control gating. CLOCK,
RESET, DATA, PRESET ENABLE, and 5 individual
JAM inputs are provided. Divide by 10, 8, 6, 4, or 2
counter configurations can be implemented by feed-
ing the Q5, Q4, Q3, Q2, Q1 signals, respectively,
back to the DATA input.
Divide-by-9, 7, 5, or 3 counter configurations can be
implemented by the use of a HCC/HCF4011B gate
package to properly gate the feedback connection
to the DATA input. Divide-by-functions greater than
10 can be achieved by use of multiple HCC/HCF
4018B units. The counter is advanced one count at
the positive clock-signal transition. Schmitt Trigger
action on the clock line permits unlimited clock rise
and fall times. A high RESET signal clears the
counter to an all-zero condition. A high PRESENT-
ENABLE signal allows information on the JAM in-
puts to preset the counter. Anti-lock gating is
provided to assure the proper counting sequence.
June 1989
PIN CONNECTIONS
1/12
1 page  
HCC/HCF4018B
DYNAMIC ELECTRICAL CHARACTERISTICS (T amb = 25°C, CL = 50pF, RL = 200kΩ,
typical temperature coefficient for all VDD values is 0.3%/°C, all input rise and fall times = 20ns)
Symbol
Parameter
t PL H, t PHL Propagation Delay Time
Test Conditions
V al ue
V D D (V) Min. Typ. Max.
5 200 400
10 90 180
15 65 130
t T HL, t TL H Transition Time
5 100 200
10 50 100
15 40 80
fCL Maximum Clock Input Frequency
5 36
10 7 14
15 8.5 17
tW Clock Input Width
5 160 80
10 70 35
15 50 25
tr, tf Clock Input Rise or Fall Time
5
10 Unlimited
15
t s e t u p Data Input Set-up Time
5 40 20
10 12 6
15 6 3
t H Data Input Hold-time
5 140 70
10 80 40
15 60 30
PRESET* OR RESET OPERATION
t PL H, t PHL Propagation Delay Time
(reset or reset to Q)
5 275 550
10 125 250
15 90 180
tW Preset or Reset Pulse Width
5 160 80
10 70 35
15 50 25
tre m Preset or Reset Removal Time
5 80 40
10 30 15
15 20 10
• At PRESET ENABLE OR JAM inputs
Unit
ns
ns
MHz
ns
µs
ns
ns
ns
ns
ns
5/12
5 Page 
DIM.
A
B
D
d1
d2
E
e
e3
F
G
M
M1
HCC/HCF4018B
MIN.
9.78
8.89
4.2
7.37
PLCC20 MECHANICAL DATA
mm
TYP.
2.54
0.56
1.27
5.08
0.38
1.27
1.14
MAX.
10.03
9.04
4.57
MIN.
0.385
0.350
0.165
8.38 0.290
0.101
inch
TYP.
0.100
0.022
0.050
0.200
0.015
0.050
0.045
MAX.
0.395
0.356
0.180
0.330
0.004
P027A
11/12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet HCC4018.PDF ] | |
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