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PDF HCC40101BF Data sheet ( Hoja de datos )

Número de pieza HCC40101BF
Descripción 9-BIT PARITY GENERATOR/CHECKER
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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No Preview Available ! HCC40101BF Hoja de datos, Descripción, Manual

HCC/HCF40101B
9-BIT PARITY GENERATOR/CHECKER
. STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
. QUIESCENT CURRENT SPECIFIED AT 20V
FOR HCC DEVICE
. 5V, 10V, AND 15V PARAMETRIC RATINGS
. INPUT CURRENT OF 100nA AT 18V AND 25°C
FOR HCC DEVICE
. 100% TESTED FOR QUIESCENT CURRENT
. MEETS ALL REQUIREMENTS OF JEDECTEN-
TATIVE STANDARD N° 13A, ”STANDARD SPE-
CIFICATIONS FOR DESCRIPTION OF ”B”
SERIES CMOS DEVICES”
EY F
(Plastic Package) (Ceramic Frit Seal Package)
M1
(Micro Package)
C1
(Plastic Chip Carrier)
ORDER CODES :
HCC40101BF
HCF40101BM1
HCF40101BEY HCF40101BC1
PIN CONNECTIONS
DESCRIPTION
The HCC40101B (extended temperature range)
and HCF40101B (intermediate temperature range)
are monolithic integrated circuits, available in 14-
lead dual in-line plastic or ceramic package and
plastic micro package.
The HCC/HCF40101B is a 9-bit (8 data bits plus 1
parity bit) parity generator/checker. It may be used
to detect errors in data transmission or data retrie-
val. Odd and even outputs facilitate odd or even
parity generation and checking. When used as a
parity generator, a parity bit is supplied along with
the data to generate an even or odd parity output.
When used a parity checker, the received data bits
and parity bits are compared for correct parity. The
even or odd outputs are used to indicate an error in
the received data. Word-length capability is expan-
dable by cascading. The HCC/HCF40101B is also
provided with an inhibit control. If the inhibit control
is set at logical ”1”, the even and odd outputs go to
a logical ”0”.
June 1989
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HCC40101BF pdf
HCC/HCF40101B
DYNAMIC ELECTRICAL CHARACTERISTICS (T amb = 25°C, CL = 50pF, RL = 200k,
typical temperature coefficient for all VDD values is 0.3%/°C, all input rise and fall time = 20ns)
Symbol
Parameter
t PLH,
tP HL
Propagation Delay Time
Test Conditions
V al ue
V D D (V) Min. Typ. Max.
5 350 700
10 150 300
15 100 200
t PLH,
tP HL
Propagation Delay Time
Inhibit to Output
5 140 280
10 70 140
15 50 100
t T L H,
tT HL
Transition Time
5 100 200
10 50 100
15 40 80
Unit
ns
ns
ns
Output Low (sink) Current Characteristics.
Output High (source) Current Characteristics.
Typical Propagation Delay Time vs. Load Capacit-
ance.
Typical Transition Time vs. Load Capacitance.
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HCC40101BF arduino
HCC/HCF40101B
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
© 1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A
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