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HC74 の電気的特性と機能

HC74のメーカーはSystem Logic Semiconductorです、この部品の機能は「Dual D Flip-Flop with Set and Reset(High-Performance Silicon-Gate CMOS)」です。


製品の詳細 ( Datasheet PDF )

部品番号 HC74
部品説明 Dual D Flip-Flop with Set and Reset(High-Performance Silicon-Gate CMOS)
メーカ System Logic Semiconductor
ロゴ System Logic Semiconductor ロゴ 




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HC74 Datasheet, HC74 PDF,ピン配置, 機能
SL74HC74
Dual D Flip-Flop with Set and Reset
High-Performance Silicon-Gate CMOS
The SL74HC74 is identical in pinout to the LS/ALS74. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device consists of two D flip-flops with individual Set, Reset,
and Clock inputs. Information at a D-input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q outputs are available from each flip-flop. The Set
and Reset inputs are asynchronous.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC74N Plastic
SL74HC74D SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 14 =VCC
PIN 7 = GND
SLS
System Logic
Semiconductor
FUNCTION TABLE
Inputs
Outputs
Set Reset Clock Data Q
Q
LH X XHL
HL X XLH
L L X X H* H*
HH
HH L
HH
L LH
H H L X No Change
H H H X No Change
HH
X No Change
*Both outputs will remain high as long as Set
and Reset are low, but the output states are
unpredictable if Set and Reset go high
simultaneously.
X = don’t care

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HC74 pdf, ピン配列
SL74HC74
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
Symbol
Parameter
Test Conditions
VIH Minimum High-Level VOUT=0.1 V or VCC-0.1 V
Input Voltage
IOUT≤ 20 µA
VIL Maximum Low -Level VOUT=0.1 V or VCC-0.1 V
Input Voltage
IOUT ≤ 20 µA
VOH Minimum High-Level VIN=VIH or VIL
Output Voltage
IOUT ≤ 20 µA
VIN=VIH or VIL
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA
VOL Maximum Low-Level VIN=VIH or VIL
Output Voltage
IOUT ≤ 20 µA
VIN=VIH or VIL
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA
IIN Maximum Input
Leakage Current
VIN=VCC or GND
ICC Maximum Quiescent VIN=VCC or GND
Supply Current
IOUT=0µA
(per Package)
VCC Guaranteed Limit
V 25 °C 85 125
to °C °C
-55°C
2.0 1.5 1.5 1.5
4.5 3.15 3.15 3.15
6.0 4.2 4.2 4.2
2.0 0.5 0.5 0.5
4.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8
2.0 1.9
4.5 4.4
6.0 5.9
1.9 1.9
4.4 4.4
5.9 5.9
4.5 3.98 3.84 3.7
6.0 5.48 5.34 5.2
2.0 0.1
4.5 0.1
6.0 0.1
0.1 0.1
0.1 0.1
0.1 0.1
4.5 0.26 0.33 0.4
6.0 0.26 0.33 0.4
6.0 ±0.1 ±1.0 ±1.0
6.0 2.0 20 80
Unit
V
V
V
V
µA
µA
SLS
System Logic
Semiconductor


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共有リンク

Link :


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