DataSheet.jp

UPD42S17405LA-50 の電気的特性と機能

UPD42S17405LA-50のメーカーはNECです、この部品の機能は「16M-BIT DYNAMIC RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD42S17405LA-50
部品説明 16M-BIT DYNAMIC RAM
メーカ NEC
ロゴ NEC ロゴ 




このページの下部にプレビューとUPD42S17405LA-50ダウンロード(pdfファイル)リンクがあります。
Total 30 pages

No Preview Available !

UPD42S17405LA-50 Datasheet, UPD42S17405LA-50 PDF,ピン配置, 機能
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD42S17405, 4217405
16 M-BIT DYNAMIC RAM
4 M-WORD BY 4-BIT, EDO
Description
The µPD42S17405, 4217405 are 4,194,304 words by 4 bits CMOS dynamic RAMs with optional EDO.
EDO is a kind of the page mode and is useful for the read operation.
Besides, the µPD42S17405 can execute CAS before RAS self refresh.
The µPD42S17405, 4217405 are packaged in 26-pin plastic TSOP (II) and 26-pin plastic SOJ.
Features
• EDO (Hyper page mode)
• 4,194,304 words by 4 bits organization
• Single +5.0 V ±10 % power supply
• Fast access and cycle time
Part number
µPD42S17405-50, 4217405-50
µPD42S17405-60, 4217405-60
µPD42S17405-70, 4217405-70
Power
consumption
Active (MAX.)
660 mW
605 mW
550 mW
Access time
(MAX.)
R/W cycle time
(MIN.)
50 ns
60 ns
70 ns
84 ns
104 ns
124 ns
EDO (Hyper page mode)
cycle time (MIN.)
20 ns
25 ns
30 ns
µPD42S17405 can execute CAS before RAS self refresh
Part number
µPD42S17405
Refresh cycle
2,048 cycles/128 ms
µPD4217405
2,048 cycles/32 ms
Refresh
CAS before RAS self refresh
CAS before RAS refresh
RAS only refresh
Hidden refresh
CAS before RAS refresh
RAS only refresh
Hidden refresh
Power consumption
at standby (MAX.)
1.4 mW
(CMOS level input)
5.5 mW
(CMOS level input)
The information in this document is subject to change without notice.
Document No. M10067EJ6V0DS00 (6th edition)
Date Published January 1997 N
Printed in Japan
The mark shows major revised points.
©
1995

1 Page





UPD42S17405LA-50 pdf, ピン配列
Pin Configurations (Marking Side)
26-pin Plastic TSOP (II) (300 mil)
VCC
I/O1
I/O2
WE
RAS
NC
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
8
9
10
11
12
13
26 GND
25 I/O4
24 I/O3
23 CAS
22 OE
21 A9
19 A8
18 A7
17 A6
16 A5
15 A4
14 GND
µPD42S17405, 4217405
26-pin Plastic SOJ (300 mil)
VCC
I/O1
I/O2
WE
RAS
NC
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
8
9
10
11
12
13
26 GND
25 I/O4
24 I/O3
23 CAS
22 OE
21 A9
19 A8
18 A7
17 A6
16 A5
15 A4
14 GND
A0 to A10 : Address Inputs
I/O1 to I/O4: Data Inputs/Outputs
RAS
: Row Address Strobe
CAS
: Column Address Strobe
WE : Write Enable
OE : Output Enable
VCC : Power Supply
GND
: Ground
NC : No Connection
3


3Pages


UPD42S17405LA-50 電子部品, 半導体
µPD42S17405, 4217405
Hyper Page Mode (EDO)
The hyper page mode (EDO) is a kind of page mode with enhanced features. The two major features of the
hyper page mode (EDO) are as follows.
1. Data output time is extended.
In the hyper page mode (EDO), the output data is held to the next CAS cycle’s falling edge, instead of the rising
edge. For this reason, valid data output time in the hyper page mode (EDO) is extended compared with the fast
page mode (= data extend function). In the fast page mode, the data output time becomes shorter as the CAS
cycle time becomes shorter. Therefore, in the hyper page mode (EDO), the timing margin in read cycle is larger
than that of the fast page mode even if the CAS cycle time becomes shorter.
2. The CAS cycle time in the hyper page mode (EDO) is shorter than that in the fast page mode.
In the hyper page mode (EDO), due to the data extend function, the CAS cycle time can be shorter than in the
fast page mode if the timing margin is the same.
Taking a device whose tRAC is 60 ns as an example, the CAS cycle time in the fast page mode is 25 ns while that
in the fast page mode is 40 ns.
In the hyper page mode (EDO) , read (data out) and write (data in) cycles can be executed repeatedly during one
RAS cycle. The hyper page mode (EDO) allows both read and write operations during one cycle.
The following shows a part of the hyper page mode (EDO) read cycle. Specifications to be observed are described
in the next page.
VIH
RAS VIL
Hyper Page Mode (EDO) Read Cycle
tHPC
tOFR
VIH
CAS VIL
tOFC
Address VIH
VIL
VIH
WE
VIL
VIH
OE VIL
I/O
VOH
VOL
Row
Col.A
tRAC
tAA
tCAC
tOCH
tOEA
Col.B
tAA
tCAC
Col.C
tAA
tCAC
tRRH
tRCH
tWPZ
tCHO
tOEP
tOCH
tOEP
tOEA
tCHO
tWEZ
Hi - Z
tOLZ
tCLZ
tDHC
tOEZ
tCLZ tOEZ
tOEZ
Data out A
Data out B
Data out C
Data out C Hi - Z
6

6 Page



ページ 合計 : 30 ページ
 
PDF
ダウンロード
[ UPD42S17405LA-50 データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
UPD42S17405LA-50

16M-BIT DYNAMIC RAM

NEC
NEC


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap