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HC123 の電気的特性と機能

HC123のメーカーはFairchild Semiconductorです、この部品の機能は「Dual Retriggerable Monostable Multivibrator」です。


製品の詳細 ( Datasheet PDF )

部品番号 HC123
部品説明 Dual Retriggerable Monostable Multivibrator
メーカ Fairchild Semiconductor
ロゴ Fairchild Semiconductor ロゴ 




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HC123 Datasheet, HC123 PDF,ピン配置, 機能
July 1993
Revised April 1999
74VHC123A
Dual Retriggerable Monostable Multivibrator
General Description
The VHC123A is an advanced high speed CMOS
Monostable Multivibrator fabricated with silicon gate CMOS
technology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. Each multivibrator features
both a negative, A, and a positive, B, transition triggered
input, either of which can be used as an inhibit input. Also
included is a clear input that when taken low resets the
one-shot. The VHC123A can be triggered on the positive
transition of the clear while A is held low and B is held high.
The output pulse width is determined by the equation:
PW = (Rx)(Cx); where PW is in seconds, R is in ohms, and
C is in farads.
Limits for Rx and Cx are:
External capacitor, Cx No limit
External resistors, Rx VCC = 2.0V, 5 kmin
VCC > 3.0V, 1 kmin
An input protection circuit ensures that 0 to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery back up. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s High Speed:
tPD = 8.1 ns (typ) at TA = 25°C
s Low Power Dissipation:
ICC = 4 µA (Max) at TA = 25°C
s Active State: ICC = 600 µA (Max) at TA = 25°C
s High Noise Immunity: VNIH = VNIL = 28% VCC (min)
s Power down protection is provided on all inputs
s Pin and function compatible with 74HC123A
Ordering Code:
Order Number Package Number
Package Description
74VHC123AM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
74VHC123ASJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC123AMTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC123AN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS011621.prf
www.fairchildsemi.com

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HC123 pdf, ピン配列
Timing Chart
Functional Description
1. Stand-by State
The external capacitor (Cx) is fully charged to VCC in
the Stand-by State. That means, before triggering, the
QP and QN transistors which are connected to the Rx/
Cx node are in the off state. Two comparators that
relate to the timing of the output pulse, and two refer-
ence voltage supplies turn off. The total supply current
is only leakage current.
2. Trigger Operation
Trigger operation is effective in any of the following
three cases. First, the condition where the A input is
LOW, and B input has a rising signal; second, where
the B input is HIGH, and the A input has a falling signal;
and third, where the A input is LOW and the B input is
HIGH, and the CLR input has a rising signal.
After a trigger becomes effective, comparators C1 and
C2 start operating, and QN is turned on. The external
capacitor discharges through QN. The voltage level at
the Rx/Cx node drops. If the Rx/Cx voltage level falls to
the internal reference voltage VrefL, the output of C1
becomes LOW. The flip-flop is then reset and QN turns
off. At that moment C1 stops but C2 continues operat-
ing.
After QN turns off, the voltage at the Rx/Cx node starts
rising at a rate determined by the time constant of
external capacitor Cx and resistor Rx.
Upon triggering, output Q becomes HIGH, following
some delay time of the internal F/F and gates. It stays
HIGH even if the voltage of Rx/Cx changes from falling
to rising. When Rx/Cx reaches the internal reference
voltage VrefH, the output of C2 becomes LOW, the out-
put Q goes LOW and C2 stops its operation. That
means, after triggering, when the voltage level of the
Rx/Cx node reaches VrefH, the IC returns to its
MONOSTABLE state.
With large values of Cx and Rx, and ignoring the dis-
charge time of the capacitor and internal delays of the
IC, the width of the output pulse, tW (OUT), is as fol-
lows:
tW (OUT) = 1.0 Cx Rx
3. Retrigger operation (74VHC123A)
When a new trigger is applied to either input A or B
while in the MONOSTABLE state, it is effective only if
the IC is charging Cx. The voltage level of the Rx/Cx
node then falls to VrefL level again. Therefore the Q
output stays HIGH if the next trigger comes in before
the time period set by Cx and Rx.
If the new trigger is very close to a previous trigger,
such as an occurrence during the discharge cycle, it
will have no effect.
The minimum time for a trigger to be effective 2nd trig-
ger, tRR (Min), depends on VCC and Cx.
4. Reset Operation
In normal operation, the CLR input is held HIGH. If
CLR is LOW, a trigger has no affect because the Q out-
put is held LOW and the trigger control F/F is reset.
Also, Qp turns on and Cx is charged rapidly to VCC.
This means if CLR is set LOW, the IC goes into a wait
state.
3 www.fairchildsemi.com


3Pages


HC123 電子部品, 半導体
Device Characteristics
twout*Cx Characteristics (typ)
tRR*VCC Characteristics (typ)
Output Pulse Width Constant K-Supply Voltage
(Typical)
Input Equivalent Circuit
www.fairchildsemi.com
6

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