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HC-5560 の電気的特性と機能

HC-5560のメーカーはIntersil Corporationです、この部品の機能は「PCM Transcoder」です。


製品の詳細 ( Datasheet PDF )

部品番号 HC-5560
部品説明 PCM Transcoder
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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HC-5560 Datasheet, HC-5560 PDF,ピン配置, 機能
Data Sheet
HC-5560
January 1997 File Number 2887.2
PCM Transcoder
The HC-5560 digital line transcoder provides encoding and
decoding of pseudo ternary line code substitution schemes.
Unlike other industry standard transcoders, the HC-5560
provides four worldwide compatible mode selectable code
substitution schemes, including HDB3 (High Density Bipolar
3), B6ZS, B8ZS (Bipolar with 6 or 8 Zero Substitution) and
AMI (Alternate Mark Inversion).
The HC-5560 is fabricated in CMOS and operates from a
single 5V supply. All inputs and outputs are TTL compatible.
Application Note #573, “The HC-5560 Digital Line
Transcoder,” by D.J. Donovan is available.
Ordering Information
PART TEMP. RANGE
NUMBER (oC) PACKAGE
PKG. NO.
HC3-5560-5
0 to 70 20 Ld PDIP E20.3
Pinout
HC-5560
(PDIP)
TOP VIEW
FORCE AIS 1
MODE SELECT 1 2
NRZ DATA IN 3
CLK ENC 4
MODE SELECT 2 5
NRZ DATA OUT 6
CLK DEC 7
RESET AIS 8
AIS 9
VSS 10
20 VDD
19 OUTPUT ENABLE
18 RESET
17 OUT1
16 OUT2
15 BIN
14 LOOP TEST ENABLE
13 AIN
12 CLOCK
11 ERROR
Features
• Single 5V Supply . . . . . . . . . . . . . . . . . . . . . . .10mA (Typ)
• Mode Selectable Coding Including:
- AMI (T1, T1C)
- B8ZS (T1)
- HDB3 (PCM30)
• North American and European Compatibility
• Simultaneous Encoding and Decoding
• Asynchronous Operation
• Loop Back Control
• Transmission Error Detection
• Alarm Indication Signal
• Replaces MJ1440, MJ1471 and TCM2201 Transcoders
Applications
• North American and European PCM Transmission Lines
where Pseudo Ternary Line Code Substitution Schemes
are Desired
• Any Equipment that Interfaces T1, T1C, T2 or PCM30
Lines Including Multiplexers, Channel Service Units,
(CSUs) Echo Cancellors, Digital Cross-Connects (DSXs),
T1 Compressors, etc.
• Related Literature
- AN573, The HC-5560 Digital Line Transcoder
Functional Diagram
MODE 1
SELECT 2
NRZ DATA IN
CLK ENC
OUTPUT
ENABLE
TRANSMITTER/
ENCODER
VDD
VSS
CLOCK
OUT 1
OUT 2
LOOP TEST
ENABLE
AIN
BIN
FORCE AIS
RESET
CLK DEC
RESET AIS
SWITCH
RECEIVER/
DECODER
NRZ DATA
OUT
AIS
DETECT
ERROR
DETECT
ERROR
AIS
69 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999

1 Page





HC-5560 pdf, ピン配列
HC-5560
Electrical Specifications Unless Otherwise Specified, Typical parameters at 25oC, Min-Max parameters are over operating
temperature range. VDD = 5V (Continued)
PARAMETER
NRZ-Data In to CLK ENC Data Setup Time
Data Hold Time
AIN, BIN to CLK DEC Data Setup Time
Data Hold Time
CLK ENC to OUT1, OUT2
OUT1, OUT2 Pulse Width (CLK ENC Duty Cycle = 50%)
fCL = 1.544MHz
fCL = 2.048MHz
fCL = 6.3212MHz
fCL = 8.448MHz
CLK DEC to NRZ-Data Out
Setup Time CLK DEC to Reset AlS
Hold Time of Reset AlS = ‘0’
Setup Time Reset AlS = ‘1’ to CLK DEC
Reset AlS to AIS output
CLK DEC to Error output
Pin Descriptions
SYMBOL
FIGURE
MIN
TYP
MAX
UNITS
tS
1
20 -
- ns
tH
1
20 -
- ns
tS
2
15 -
- ns
tH 2 5 - - ns
tDD 1
- 23 80 ns
tW
1
- 324 -
ns
tW
1
- 224 -
ns
tW 1 - 79 - ns
tW 1 - 58 - ns
tDD 2
- 25 54 ns
tS2
3
35 -
- ns
tH2
3
20 -
- ns
tS2 3 0 - - ns
tPD5
3
- - 42 ns
tPD4
3
- - 62 ns
PIN NUMBER
1
2, 5
3
4
6
7
8, 9
10
11
12
13, 15
FUNCTION
Force AIS
Mode Select 1,
Mode Select 2
NRZ Data In
CLK ENC
NRZ Data Out
CLK DEC
Reset AIS, AlS
VSS
Error
Clock
AIN, BIN
DESCRIPTION
Pin 19 must be at logic ‘0’ to enable this pin. A logic ‘1’ on this pin forces OUT1 and OUT2 to all ‘1’s. A logic
‘0’ on this pin allows normal operation.
MS1
0
0
1
1
MS2
0
1
0
1
Functions As
AMI
B8ZS
B6ZS
HDB3
Input data to be encoded into ternary form. The data is clocked by the negative going edge of CLK ENC.
Clock encoder, clock for encoding data at NRZ Data In.
Decoded data from ternary inputs AIN and BIN.
Clock decoder, clock for decoding ternary data on inputs AIN and BIN.
Logic ‘0’ on Reset AIS resets a decoded zero counter and either resets AIS output to zero provided 3 or more
zeros have been decoded in the preceding Reset AIS period or sets AlS to ‘1’ if less than 3 zeros have been
decoded in the preceding two Reset AlS periods. A period of Reset AlS is defined from the bit following the
bit during which Reset AlS makes a high to low transition to the bit during which Reset AIS makes the next
high to low transition.
Ground reference.
A logic ‘1’ indicates that a violation of the line coding scheme has been decoded.
“OR” function of AIN and BIN for clock regeneration when pin 14 is at logic ‘0’, “OR” function of OUT1 and
OUT2 when pin 14 is at logic ‘1’.
Inputs representing the received PCM signal. AIN = ‘1’ represents a positive going ‘1’ and BIN = ‘1’ represents
a negative going ‘1’. AIN and BIN are sampled by the positive going edge of CLK DEC. AIN and BIN may be
interchanged.
71


3Pages


HC-5560 電子部品, 半導体
Application Diagram
FROM CODEC OR
TRANSCODER
ENCODER CLOCK
HC-5560
5V
VDD
NRZ DATA IN
ENCODER
CLK ENC
OUT1
OUT2
LINE
INPUT
DIFF
AMP
V+
FORCE AIS
MS1
LTE CONTROL MS2
RESET
OUTPUT
ENABLE
CLOCK
RESET AIS
AIS
ERROR
± AIN DECODER
NRZ DATA OUT
± BIN
CLK DEC VSS
DECODER CLOCK
T1, T2, T1C,
V+ PCM 30
LINE OUTPUT
MODE SELECT
LOGIC INPUTS
CLOCK RECOVERY
ALARM CLOCK
ALARM
ERROR
ERROR
MONITORS
TO CODED OR TRANSCODER
MS1 MS2 SELECTS
00
AMI
0 1 B8ZS
1 0 B6ZS
1 1 HDB3
Timing Waveforms
tRCL
CLK ENC 10%
NRZ DATA IN
1
fCL
tFCL
90%
tS
50%
50%
tH
50%
OUT 1, OUT 2
tDD
50%
50%
tW
FIGURE 1. TRANSMITTER (CODER) TIMING WAVEFORMS
74

6 Page



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部品番号部品説明メーカ
HC-5560

PCM Transcoder

Intersil Corporation
Intersil Corporation


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