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PDF MT72KSZS2G72LZ Data sheet ( Hoja de datos )
| Número de pieza | MT72KSZS2G72LZ | |
| Descripción | DDR3L 1.35V SDRAM LRDIMM | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
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16GB, 32GB (x72, ECC, QR) 240-Pin DDR3L 1.35V LRDIMM
Features
DDR3L 1.35V SDRAM LRDIMM
MT72KSZS2G72LZ – 16GB
MT72KSZS4G72LZ – 32GB
Features
• 240-pin, load-reduced dual in-line memory module
(LRDIMM)
• Memory buffer (MB)
• Fast data transfer rates: PC3-10600, PC3-8500, or
PC3-6400
• 16GB (2 Gig x 72), 32GB (4 Gig x 72)
• VDD = 1.35V (1.283V to 1.45V)
• Backwards-compatible to VDD = 1.5V ±0.075V
• VDDSPD = 3.0–3.6V
• Supports ECC error detection and correction
• Nominal and dynamic on-die termination (ODT) for
data and strobe signals
• Quad rank, using 4Gb or 8Gb TwinDie™ devices
• 8 internal device banks
• Fixed burst chop (BC) of 4 and burst length (BL) of 8
via the mode register set (MRS)
• Two on-board temperature sensors
• Gold edge contacts
• Heat spreader
• Halogen-free
• Single load on DQ and DQS
• Terminated control, command, and address bus
Figure 1: 240-Pin LRDIMM (RC/C) MO-269
Module Height: 30.35mm (1.195 in.)
Options
• Operating temperature
– Commercial (0°C ≤ TC ≤ +95°C)
• Package
– 240-pin DIMM (halogen-free)
• Frequency/CAS latency
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.87ns @ CL = 7 (DDR3-1066)
Marking
None
Z
-1G4
-1G1
Table 1: Key Timing Parameters
Speed
Grade
-1G4
-1G1
-1G0
-80B
Industry
Nomenclature
PC3-10600
PC3-8500
PC3-8500
PC3-6400
CL = 10
1333
–
–
–
CL = 9
1333
–
–
–
Data Rate (MT/s)
CL = 8 CL = 7
1066
1066
1066
1066
1066
–
––
CL = 6
800
800
800
800
CL = 5
667
667
667
667
tRCD
(ns)
13.125
13.125
15
15
tRP
(ns)
13.125
13.125
15
15
tRC
(ns)
49.125
50.625
52.5
52.5
PDF: 09005aef8410dd71
kszs72c2g_4gx72lz.pdf Rev. C 9/11 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1 page  
16GB, 32GB (x72, ECC, QR) 240-Pin DDR3L 1.35V LRDIMM
Pin Descriptions
Table 6: Pin Descriptions (Continued)
Symbol
SDA
TDQSx,
TDQSx#
Err_Out#
EVENT#
VDD
VDDSPD
VREFCA
VREFDQ
VSS
VTT
NC
NF
Type
I/O
Output
Output
(open drain)
Output
(open drain)
Supply
Supply
Supply
Supply
Supply
Supply
–
–
Description
Serial data: Used to transfer addresses and data into and out of the temperature sen-
sor/SPD EEPROM on the I2C bus.
Redundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD
MODE command to the extended mode register (EMR). When TDQS is enabled, DM is
disabled and TDQS and TDQS# provide termination resistance; otherwise, TDQS# are
no function.
Parity error output: Parity error found on the command and address bus.
Temperature event:The EVENT# pin is asserted by the temperature sensor when criti-
cal temperature thresholds have been exceeded.
Power supply: 1.35V (1.283–1.45V) backward-compatible to 1.5V (1.425–1.575V). The
component VDD and VDDQ are connected to the module VDD.
Temperature sensor/SPD EEPROM power supply: 3.0–3.6V.
Reference voltage: Control, command, and address VDD/2.
Reference voltage: DQ, DM VDD/2.
Ground.
Termination voltage: Used for control, command, and address VDD/2.
No connect: These pins are not connected on the module.
No function: These pins are connected within the module, but provide no functional-
ity.
PDF: 09005aef8410dd71
kszs72c2g_4gx72lz.pdf Rev. C 9/11 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
5 Page 
16GB, 32GB (x72, ECC, QR) 240-Pin DDR3L 1.35V LRDIMM
General Description
Temperature Sensor
Parity Operations
registers can be read by software from the SMBus host any time the memory buffer is
powered, except when the memory buffer is in clock-stopped power-down mode, or
when the device RESET# pin is asserted.
The memory buffer contains a class-C temperature sensor that can be configured to as-
sert the EVENT# pin when temperature thresholds are exceeded. The temperature sen-
sor is accessible through the SMBus.
The memory buffer can accept a parity bit from the system’s memory controller, pro-
viding even parity for the control, command, and address bus. Parity is calculated from
all command and address signals (CKE, ODT, and S# are not included in parity). The last
bit of the sum is compared to the parity signal provided by the system at the Par_In pin.
Parity errors are flagged on the Err_Out# pin. Parity is also checked during control-word
programming.
Serial Presence-Detect EEPROM with Temperature Sensor
Serial Presence-Detect EEPROM Operation
DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to comply with
JEDEC standard JC-45, “Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM
Modules.” These bytes identify module-specific timing parameters, configuration infor-
mation, and physical attributes. User-specific information can be written into the re-
maining 128 bytes of storage. READ/WRITE operations between the system (master)
and the EEPROM (slave) device occur via the SMBus. Write-protect (WP) is connected
to VSS, permanently disabling hardware write-protect. For further information please
refer to Micron technical note TN-04-42, "Memory Module Serial Presence-Detect."
Temperature Sensor
A class-B temperature sensor is integrated with the SPD EEPROM component on the
module. The sensor temperature is monitored and converted into a digital word via the
SMBus. System designers can use the user-programmable registers to create a custom
temperature-sensing solution based on system requirements. Programming and config-
uration details comply with JEDEC standard No. 21-C page 4.7-1, “Definition of the
TSE2002av, Serial Presence Detect with Temperature Sensor.”
PDF: 09005aef8410dd71
kszs72c2g_4gx72lz.pdf Rev. C 9/11 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
11 Page | ||
| Páginas | Total 18 Páginas | |
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