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STU419SのメーカーはSamHop Microelectronicsです、この部品の機能は「P-Channel Logic Level Enhancement Mode Field Effect Transistor」です。 |
部品番号 | STU419S |
| |
部品説明 | P-Channel Logic Level Enhancement Mode Field Effect Transistor | ||
メーカ | SamHop Microelectronics | ||
ロゴ | |||
このページの下部にプレビューとSTU419Sダウンロード(pdfファイル)リンクがあります。 Total 8 pages
STU/D419SGreen
Product
Sa mHop Microelectronics C orp.
P-Channel Logic Level Enhancement Mode Field Effect Transistor
Ver 1.0
PRODUCT SUMMARY
VDSS
ID RDS(ON) (mΩ) Max
-40V
-58A
11.5 @ VGS=10V
16 @ VGS=4.5V
FEATURES
Super high dense cell design for low RDS(ON).
Rugged and reliable.
Suface Mount Package.
ESD Protected.
G
S
STU SERIES
TO - 252AA( D- PAK )
G
DS
STD SERIES
TO - 251( I - PAK )
ABSOLUTE MAXIMUM RATINGS (TA=25°C unless otherwise noted)
Symbol Parameter
VDS Drain-Source Voltage
VGS Gate-Source Voltage
Drain Current-Continuous(Package limited) TC=25°C
ID
-Continuous(Silicon limited)
TC=25°C
-Continuous a
TA=25°C
IDM -Pulsed b
EAS Sigle Pulse Avalanche Energy d
Maximum Power Dissipation
PD Maximum Power Dissipation a
TC=25°C
TA=25°C
TJ, TSTG
Operating Junction and Storage
Temperature Range
THERMAL CHARACTERISTICS
R JC
Thermal Resistance, Junction-to-Case
R JA
Thermal Resistance, Junction-to-Ambient a
Limit
-40
±20
-50
-58
-11
-175
224
70
2.5
-55 to 150
1.8
50
Units
V
V
A
A
A
A
mJ
W
W
°C
°C/W
°C/W
Details are subject to change without notice.
1
Sep,15,2008
www.samhop.com.tw
1 Page STU/D419S
25
V GS =-10V
20
V GS =-4.5V
15
V GS =-2.5V
10
5
V GS =-2V
0
0 0.5 1 1.5 2 2.5 3
-VDS, Drain-to-Source Voltage(V)
Figure 1. Output Characteristics
Ver 1.0
20
15
10
5
-55 C
1
T j=125 C
25 C
0
0 0.5 1.0 1.5 2.0 2.5 3.0
-VGS, Gate-to-Source Voltage(V)
Figure 2. Transfer Characteristics
24
20
16
V GS =4.5V
12
8 V GS =10V
4
0
1 5 10 15 20 25
-ID, Drain Current(A)
Figure 3. On-Resistance vs. Drain Current
and Gate Voltage
1.8
1.6
V G S =-10V
1.4 ID=-20A
V G S =-4V
1.2 ID=-17A
1.0
0.8
0
25 50 75 100 125 150
T j( C )
Tj, Junction Temperature(°C )
Figure 4. On-Resistance Variation with Drain
Current and Temperature
1.6
1.4
V DS =V G S
ID=-250uA
1.2
1.0
0.8
0.6
0.4
0.2
-50 -25 0 25 50 75 100 125 150
Tj, Junction Temperature(°C )
Figure 5. Gate Threshold Variation
with Temperature
1.15
1.10 ID=-250uA
1.05
1.00
0.95
0.90
0.85
-50 -25 0 25 50 75 100 125 150
Tj, Junction Temperature(°C )
Figure 6. Breakdown Voltage Variation
with Temperature
Sep,15,2008
3 www.samhop.com.tw
3Pages STU/D419S
PACKAGE OUTLINE DIMENSIONS
TO-251
E
E2
L
D1
E1 D2
D
12 3
H
B2 L2 L1
B1
A
C
Ver 1.0
D3
PB
SYMBOL
A
A1
B
B1
B2
C
D
D1
D2
D3
H
E
E1
E2
L
L1
L2
P
MILLIMETERS
MIN MAX
2.100
2.500
0.350
0.650
0.400
0.800
0.650
1.050
0.500
0.900
0.400
0.600
5.300
5.700
4.900
5.300
6.700
7.300
7.000
8.000
13.700
15.300
6.300
6.700
4.600
4.900
4.800
5.200
1.300
1.700
1.400
0.500
1.800
0.900
2.300 BSC
6
A1
INCHES
MIN MAX
0.083
0.098
0.014
0.026
0.016
0.031
0.026
0.041
0.020
0.035
0.016
0.024
0.209
0.224
0.193
0.209
0.264
0.287
0.276
0.315
0.539
0.602
0.248
0.264
0.181
0.193
0.189
0.205
0.051
0.067
0.055
0.020
0.071
0.035
0.091 BSC
Sep,15,2008
www.samhop.com.tw
6 Page | |||
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部品番号 | 部品説明 | メーカ |
STU419S | P-Channel Logic Level Enhancement Mode Field Effect Transistor | SamHop Microelectronics |