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PDF MT28F004B5 Data sheet ( Hoja de datos )
| Número de pieza | MT28F004B5 | |
| Descripción | SMART 5 BOOT BLOCK FLASH MEMORY | |
| Fabricantes | Micron Technology | |
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FLASH MEMORY
4Mb
SMART 5 BOOT BLOCK FLASH MEMORY
MT28F004B5
MT28F400B5
5V Only, Dual Supply (Smart 5)
0.3µm Process Technology
FEATURES
• Seven erase blocks:
16KB/8K-word boot block (protected)
Two 8KB/4K-word parameter blocks
Four main memory blocks
• Smart 5 technology (B5):
5V ±10% VCC
5V ±10% VPP application/production
programming
12V ±5% VPP compatibility production
programming
• Address access times: 60ns, 80ns
• 100,000 ERASE cycles
• Industry-standard pinouts
• Inputs and outputs are fully TTL-compatible
• Automated write and erase algorithm
• Two-cycle WRITE/ERASE sequence
• Byte- or word-wide READ and WRITE
(MT28F400B5, 256K x 16/512K x 8)
• Byte-wide READ and WRITE only
(MT28F004B5, 512K x 8)
• TSOP and SOP packaging options
OPTIONS
• Timing
60ns access
80ns access
80ns access
• Configurations
512K x 8
256K x 16/512K x 8
• Boot Block Starting Word Address
Top (3FFFFH)
Bottom (00000H)
• Operating Temperature Range
Commercial (0°C to +70°C)
Extended (-40°C to +85°C)
• Packages
Plastic 44-pin SOP (600 mil)
Plastic 48-pin TSOP Type 1
(12mm x 20mm)
Plastic 40-pin TSOP
(10mm x 20mm)
MARKING
-6
-8
-8 ET
MT28F004B5
MT28F400B5
T
B
None
ET
SG
WG
VG
Part Number Example:
MT28F400B5SG-8 T
40-Pin TSOP Type I 48-Pin TSOP Type I
44-Pin SOP
GENERAL DESCRIPTION
The MT28F004B5 (x8) and MT28F400B5 (x16, x8)
are nonvolatile, electrically block-erasable (flash), pro-
grammable, read-only memories containing 4,194,304
bits organized as 262,144 words (16 bits) or 524,288
bytes (8 bits). Writing or erasing the device is done with
a 5V VPP voltage, while all operations are performed
with a 5V VCC. Due to process technology advances, 5V
VPP is optimal for application and production program-
ming. For backward compatibility with SmartVoltage
technology, 12V VPP is supported for a maximum of 100
cycles and may be connected for up to 100 cumulative
hours. These devices are fabricated with Micron’s ad-
vanced CMOS floating-gate process.
The MT28F004B5 and MT28F400B5 are organized
into seven separately erasable blocks. To ensure that
critical firmware is protected from accidental erasure or
overwrite, the devices feature a hardware-protected
boot block. Writing or erasing the boot block requires
either applying a super-voltage to the RP# pin or driv-
ing WP# HIGH in addition to executing the normal
write or erase sequences. This block may be used to store
code implemented in low-level system recovery. The
remaining blocks vary in density and are written and
erased with no additional security measures.
Please refer to Micron’s Web site (www.micron.com/
flash/htmls/datasheets.html)p for the latest data sheet.
4Mb Smart 5 Boot Block Flash Memory
F44_B.p65 – Rev. 7/02
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
1 page  
4Mb
SMART 5 BOOT BLOCK FLASH MEMORY
TRUTH TABLE (MT28F400B5)1
FUNCTION
RP# CE#
Standby
HH
RESET
LX
READ
READ (word mode)
HL
READ (byte mode)
HL
Output Disable
HL
WRITE/ERASE (EXCEPT BOOT BLOCK)2
ERASE SETUP
ERASE CONFIRM3
HL
HL
WRITE SETUP
H
WRITE (word mode)4
H
WRITE (byte mode)4
H
READ ARRAY5
H
WRITE/ERASE (BOOT BLOCK)2, 7
L
L
L
L
ERASE SETUP
ERASE CONFIRM3
ERASE CONFIRM3, 6
HL
VHH L
HL
WRITE SETUP
WRITE (word mode)4
WRITE (word mode)4, 6
WRITE (byte mode)4
WRITE (byte mode)4, 6
READ ARRAY5
DEVICE IDENTIFICATION8, 9
HL
VHH L
HL
VHH L
HL
HL
Manufacturer Compatibility
(word mode)10
HL
Manufacturer Compatibility
(byte mode)
Device (word mode, top boot)10
HL
HL
Device (byte mode, top boot)
Device (word mode, bottom boot) 10
H
H
L
L
Device (byte mode, bottom boot)
HL
OE# WE# WP# BYTE# A0 A9 VPP DQ0-DQ7 DQ8-DQ14 DQ15/A - 1
X X X X X X X High-Z High-Z High-Z
X X X X X X X High-Z High-Z High-Z
L H X H X X X Data-Out Data-Out Data-Out
L H X L X X X Data-Out High-Z A - 1
H H X X X X X High-Z High-Z High-Z
H L X X XX X
20H
X
X
H L X X X X VPPH D0H
X
X
H L X X X X X 10H/40H X
X
H L X H X X VPPH Data-In Data-In Data-In
H L X L X X VPPH Data-In
X
A-1
H L X X XX X
FFH
X
X
H L X X XX X
20H
X
X
H L X X X X VPPH D0H
X
X
H L H X X X VPPH D0H
X
X
H L X X X X X 10H/40H X
X
H L X H X X VPPH Data-In Data-In Data-In
H L H H X X VPPH Data-In Data-In Data-In
H L X L X X VPPH Data-In
X
A-1
H L H L X X VPPH Data-In
X
A-1
H L X X XX X
FFH
X
X
L H X H L VID X
L H X L L VID X
L H X H H VID X
L H X L H VID X
L H X H H VID X
L H X L H VID X
89H 00H
89H High-Z
70H 44H
70H High-Z
71H 44H
71H High-Z
–
X
–
X
–
X
NOTE: 1. L = VIL (LOW), H = VIH (HIGH), X = VIL or VIH (“Don’t Care”).
2. VPPH = VPPH1 = 5V.
3. Operation must be preceded by ERASE SETUP command.
4. Operation must be preceded by WRITE SETUP command.
5. The READ ARRAY command must be issued before reading the array after writing or erasing.
6. When WP# = VIH, RP# may be at VIH or VHH.
7. VHH = 12V.
8. VID = 12V; may also be read by issuing the IDENTIFY DEVICE command.
9. A1-A8, A10-A17 = VIL.
10. Value reflects DQ8-DQ15.
4Mb Smart 5 Boot Block Flash Memory
F44_B.p65 – Rev. 7/02
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
5 Page 
4Mb
SMART 5 BOOT BLOCK FLASH MEMORY
COMMAND SET
To simplify writing of the memory blocks, the
MT28F004B5 and MT28F400B5 incorporate an ISM
that controls all internal algorithms for the WRITE and
ERASE cycles. An 8-bit command set is used to control
the device. Details on how to sequence commands are
provided in the Command Execution section. Table 1
lists the valid commands.
ISM STATUS REGISTER
The 8-bit ISM status register (see Table 2) is polled to
check for WRITE or ERASE completion or any related
errors. During or following a WRITE, ERASE or ERASE
SUSPEND, a READ operation will output the status
register contents on DQ0-DQ7 without prior com-
mand. While the status register contents are read, the
outputs will not be updated if there is a change in the
ISM status unless OE# or CE# is toggled. If the device is
not in the write, erase, erase suspend or status register
read mode, READ STATUS REGISTER (70H) can be
issued to view the status register contents.
All of the defined bits are set by the ISM, but only the
ISM and erase suspend status bits are reset by the ISM.
The erase, write and VPP status bits must be cleared
using CLEAR STATUS REGISTER. If the VPP status bit
(SR3) is set, the CEL will not allow further WRITE or
ERASE operations until the status register is cleared.
This allows the user to choose when to poll and clear
the status register. For example, the host system may
perform multiple BYTE WRITE operations before check-
ing the status register instead of checking after each
individual WRITE. Asserting the RP# signal or powering
down the device will also clear the status register.
STATUS
BIT #
SR7
SR6
SR5
SR4
SR3
STATUS REGISTER BIT
ISM STATUS
1 = Ready
0 = Busy
ERASE SUSPEND STATUS
1 = ERASE suspended
0 = ERASE in progress/completed
ERASE STATUS
1 = BLOCK ERASE error
0 = Successful BLOCK ERASE
WRITE STATUS
1 = WORD/BYTE WRITE error
0 = Successful WORD/
BYTE WRITE
VPP STATUS
1 = No VPP voltage detected
0 = VPP present
SR0-2 RESERVED
Table 2
Status Register
DESCRIPTION
The ISMS bit displays the active status of the state machine during
WRITE or BLOCK ERASE operations. The controlling logic polls this
bit to determine when the erase and write status bits are valid.
Issuing an ERASE SUSPEND places the ISM in the suspend mode
and sets this and the ISMS bit to “1.” The ESS bit will remain “1” until
an ERASE RESUME is issued.
ES is set to “1” after the maximum number of ERASE cycles is
executed by the ISM without a successful verify. ES is only cleared
by a CLEAR STATUS REGISTER command or after a RESET.
WS is set to “1” after the maximum number of WRITE cycles is
executed by the ISM without a successful verify. WS is only cleared
by a CLEAR STATUS REGISTER command or after a RESET.
VPPS detects the presence of a VPP voltage. It does not monitor VPP
continuously, nor does it indicate a valid VPP voltage. The VPP pin is
sampled for 5V after WRITE or ERASE CONFIRM is given. VPPS must be
cleared by CLEAR STATUS REGISTER or by a RESET.
Reserved for future use.
4Mb Smart 5 Boot Block Flash Memory
F44_B.p65 – Rev. 7/02
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
11 Page | ||
| Páginas | Total 32 Páginas | |
| PDF Descargar | [ Datasheet MT28F004B5.PDF ] | |
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