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ISL8126A の電気的特性と機能

ISL8126AのメーカーはIntersilです、この部品の機能は「Dual/n-Phase Buck PWM Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL8126A
部品説明 Dual/n-Phase Buck PWM Controller
メーカ Intersil
ロゴ Intersil ロゴ 




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ISL8126A Datasheet, ISL8126A PDF,ピン配置, 機能
Dual/n-Phase Buck PWM Controller with Integrated
Drivers
ISL8126
The ISL8126 integrates two voltage-mode PWM leading-edge
modulation control with input feed-forward synchronous buck
PWM controllers to control dual independent voltage
regulators or a 2-phase single output regulator. It also
integrates current sharing control for the power module to
operate in parallel, which offers high system flexibility.
The ISL8126 integrates an internal linear regulator, which
generates IC’s bias voltages for applications with only one
single supply rail. The internal oscillator is adjustable from
150kHz to 1.5MHz, and is able to synchronize to an external
clock signal for frequency synchronization and phase
paralleling applications. Its PLL circuit can output a
phase-shift-programmable clock signal for the system to be
expanded to 3-, 4-, 6-, 12- phases with desired interleaving
phase shift.
The ISL8126’s Fault Spreading feature protects any channel
from overloading/stressing due to system faults or phase
failure. The undervoltage fault protection features are also
designed to prevent a negative transient on the output voltage
during falling down. This eliminates the Schottky diode that is
used in some systems for protecting the load device from
reversed output voltage damage.
Table 1 summarizes the differences between ISL8126 and
ISL8126A.
TABLE 1.
DEVICES
ISL8126
ISL8126A
REFERENCE VOLTAGE
(V)
0.6
0.7
VSEN1+ to VSEN1- INPUT
IMPEDANCE
500kΩ
>2MΩ
Features
• Wide VIN Range Operation: 3V to 26.5V
- VCC Operation from 3V to 5.60V
• Excellent Output Voltage Regulation: 0.6V Internal
Reference
• Frequency Synchronization with Programmable Phase Delay
up to 12-Phase Applications
• Fault Spreading Capability for High System Reliability
• Digital Soft-Start with Pre-Charged Output Start-up
Capability
• Dual Independent Channel Enable Inputs with Precision
Voltage Monitor and Voltage Feed-forward Capability
- Programmable Input Voltage POR and its Hysteresis with
a Resistor Divider at EN Input
• Extensive Circuit Protection Functions: Output Overvoltage,
Undervoltage, Overcurrent Protection, Over-temperature and
Pre-Power-On-Reset Overvoltage Protection Option
Applications
• Power Supply for Datacom/Telecom and POL
• Paralleling Power Module
• Wide and Narrow Input Voltage Range Buck Regulators
Related Literature
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”
August 16, 2012
FN7892.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL8126A pdf, ピン配列
ISL8126
Functional Pin Descriptions (Continued)
PIN
NUMBER
4, 6
5
7
8
32, 10
31, 11
30, 12
SYMBOL
EN/VFF1, EN/VFF2
FSYNC
CLKOUT/REFIN
PGOOD
FB1, FB2
VMON1, VMON2
VSEN1-, VSEN2-
DESCRIPTION
These pins have triple functions. The voltage on EN/VFF_ pin is compared with a precision 0.8V threshold
for system enable to initiate soft-start. With a voltage lower than the threshold, the corresponding channel
can be disabled independently. By connecting these pins to the input rail through a voltage resistor divider,
the input voltage can be monitored for UVLO (undervoltage lockout) function. The undervoltage lockout and
its hysteresis levels can be programmed by these resistor dividers. The voltages on these pins are also fed
into the controller to adjust the sawtooth amplitude of each channel independently to realize the feed-
forward function.
Furthermore, during fault (such as overvoltage, overcurrent, and over-temperature) conditions, these pins
(EN/VFF_) are pulled low to communicate the information to other cascaded ICs.
The oscillator switching frequency is adjusted by placing a resistor (RFS) from this pin to GND. The internal
oscillator will lock to an external frequency source if this pin is connected to a switching square pulse
waveform, typically the CLKOUT signal from another ISL8126 or an external clock. The internal oscillator
synchronizes with the leading edge of the input signal.
This pin has a dual function depending on the mode in which the chip is operating. It provides a clock signal
to synchronize with other ISL8126(s) with its VSEN2- pulled within 400mV of VCC for multiphase (3-, 4-, 6-,
8-, 10-, or 12-phase) operation. When the VSEN2- pin is not within 400mV of VCC, ISL8126 is in dual mode
(dual independent PWM output). The clockout signal of this pin is not available in this mode, but the
ISL8126 can be synchronized to external clock. In dual mode, this pin works as the following two functions:
1. An external reference (0.6V target only) can be in place of the Channel 2’s internal reference through
this pin for DDR/tracking applications.
2. The ISL8126 operates as a dual-PWM controller for two independent regulators with selectable phase
degree shift, which is programmed by the voltage level on REFIN (see “DDR and Dual Mode
Operation” on page 36).
Provides an open drain Power-Good signal when both channels are within 9% of the nominal output
regulation point with 4% hysteresis (13%/9%) and soft-start complete. PGOOD monitors the outputs
(VMON1/2) of the internal differential amplifiers.
These pins are the inverting inputs of the error amplifiers. These pins should be connected to VMON1,
VMON2 with the compensation feedback network. No direct connection between FB and VMON pins is
allowed. With VSEN2- pulled within 400mV of VCC, the corresponding error amplifier is disabled and the
amplifier’s output is high impedance. FB2 is one of the two pins to determine the relative phase
relationship between the internal clock of both channels and the CLKOUT signal. See Table 2 on page 23.
These pins are outputs of the differential amplifiers. They are connected internally to the OV/UV/PGOOD
comparators. These pins should be connected to the FB1, FB2 pins by a standard feedback network when
both channels are operating independently. When VSEN1-, VSEN2- are pulled within 400mV of VCC, the
corresponding differential amplifier is disabled and its output (VMON pin) is high impedance. In such an
event, the VMON pins can be used as additional monitors of the output voltage with a resistor divider to
protect the system against single point of failure, which occurs in the system using the same resistor
divider for both of the UV/OV comparator and output voltage feedback.
These pins are the negative inputs of standard unity gain operational amplifier for differential remote
sense for the corresponding regulator (Channels 1 and 2), and should be connected to the negative rail of
the load.
When VSEN1-, VSEN2- are pulled within 400mV of VCC, the corresponding error amplifier and differential
amplifier are disabled and their outputs are high impedance. Both VSEN2+ and FB2 input signal levels
determine the relative phases between the internal controllers as well as the CLKOUT signal. See Table 2
on page 23.
When configured as multiple power modules (each module with independent voltage loop) operating in
parallel, in order to implement the current sharing control, a resistor needs to be inserted between the
VSEN1- pin and the output voltage negative sense point (between VSEN1- and lower voltage sense resistor),
as shown in the “Typical Application Circuits” “Multiple Power Modules in Parallel with Current Sharing
Control” on page 14. This introduces a correction voltage for the modules with lower load current to keep
the current distribution balanced among modules. The module with the highest load current will
automatically become the master module. The recommended value for the VSEN1- resistor is 100Ω and it
should not be large in order to keep the unit gain amplifier input impedance compatibility. A capacitor is
also recommended to place in parallel with the 100Ω.
3 FN7892.1
August 16, 2012


3Pages


ISL8126A 電子部品, 半導体
ISL8126
Integrated Driver Block Diagram
Channels 1 and 2 Gate Drive
PVCC
3
PWMn
FAULT LOGIC
GATE
CONTROL
LOGIC
SHOOT-
THROUGH
PROTECTION
BOOTn
UGATEn
10k
10k
PHASEn
LGATEn
6 FN7892.1
August 16, 2012

6 Page



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部品番号部品説明メーカ
ISL8126

Dual/n-Phase Buck PWM Controller

Intersil
Intersil
ISL8126A

Dual/n-Phase Buck PWM Controller

Intersil
Intersil


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